Methods and systems for sample rate conversion
View Patent ↗Methods and systems for sample rate conversion convert a sampled signal to a higher data rate signal. Conversion pulses are received, having a conversion rate that is higher than the sample rate of the sampled signal. Sample points are then reconstructed from the sampled signal, in real time, on either side of a conversion pulse. An interpolation is performed between the reconstructed sample points, at the time of the conversion pulse. The interpolation results are outputted in real time. The process is repeated for additional conversion pulses. The outputted interpolated amplitudes form the higher data rate signal having a data rate equal to the conversion rate. Sample rate conversion is thus performed in real time according to the higher data rate clock, rather than with fixed ratios. As a result, when the higher data rate clock is affected by, for example, jitter or other frequency variations, the higher data rate samples immediately track the lower data rate samples. This helps to insure that the output higher data rate data tracks the lower rate data, thus providing a more accurate sample rate conversion.
1. An apparatus for converting a sampled signal to a higher data rate signal, comprising:
an oscillator for generating conversion pulses having a conversion rate that is higher than a sample rate of the sampled signal; and
a processor to reconstruct from the sampled signal two sample points for each conversion pulse, interpolate between the two reconstructed sample points for each conversion pulse to form interpolated values corresponding to respective conversion pulses, and output the interpolated values, wherein the outputted interpolated values form the higher data rate signal having a data rate equal to the conversion rate.
2. The apparatus of claim 1 , wherein the processor reconstructs sample points at the conversion rate from the samples signal and identifies the two reconstructed sample points on either side of the conversion pulse.
3. The apparatus of claim 1 , wherein the processor counts a number of system clocks between a sample of the sampled signal and the conversion pulse, identifies reconstruction filter coefficients from the counted number of system clocks, and computes reconstructed sample points using the reconstruction filter coefficients.
4. The apparatus of claim 3 , wherein the processor identifies the two reconstructed sample points for each conversion pulse from a set of most significant bits of the counted number of system clocks.
5. The apparatus of claim 3 , wherein the processor identifies, from the counted number of system clocks, a relative location of the conversion pulse between the two reconstructed sample points and weights the two reconstructed sample points according to the relative location of the conversion pulse between the two identified reconstructed sample points.
6. The apparatus of claim 5 , wherein the processor identifies the relative location of the conversion pulse between the two identified reconstructed sample points, from a set of least significant bits of the counted number of system clocks.
7. The apparatus of claim 3 , wherein the counted number of system clocks is represented as a 12 bit number, wherein the 6 most significant bits of the counted number of system clocks are used to identify the two reconstructed sample points for each conversion pulse, and wherein the 6 least significant bits of the counted number of system clocks are used to interpolate between the two identified reconstructed sample points.
8. The apparatus of claim 1 , wherein the conversion rate is selectable.
9. The apparatus of claim 1 , wherein the sampled signal is a decimated composite BTSC video signal, the decimated sample rate is approximately 31.51 kHz, and the conversion rate is one of 32 kHz, 44.1 kHz, or 48 kHz.
10. The apparatus of claim 9 , wherein the conversion rate is selectable between 32 kHz, 44.1 kHz, and 48 kHz.