IP Library Granted Patent US 7,696,511
Granted Patent B2
US 7,696,511 · App. 12/186,189 · Granted Apr 13, 2010

Memory element and memory device

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,696,511
App. No.
12/186,189
Granted
Apr 13, 2010
Kind
B2
Abstract

A memory element having a storage layer containing an ion source layer between a first electrode and a second electrode is provided. The memory element stores information by changing an electrical characteristic of the storage layer, wherein at least Zr is added to the ion source layer as a metal element together with an ion conducting material.

Claims (23)

1. A memory element having a storage layer containing an ion source layer between a first electrode and a second electrode, the memory element storing information by changing an electrical characteristic of the storage layer, wherein

at least Zr is added to the ion source layer as a metal element together with an ion conducting material.

2. The memory element of claim 1 , wherein the amount of Zr contained in the ion source layer is 3 atom % or more to 40 atom % or less.

3. The memory element of claim 1 , wherein the ion source layer further contains Cu.

4. The memory element of claim 3 , wherein the ion source layer further contains Si.

5. The memory element of claim 4 , wherein the amount of Si contained in the ion source layer is from 10 atom % or more to 45 atom % or less.

6. The memory element of claim 1 , wherein the ion conducting material of the storage layer is at least one of S, Se and Te.

7. The memory element of claim 1 , wherein

a first state is stored in the memory element by applying a first voltage or a current pulse between the first electrode and the second electrode to form a conduction path containing at least the Zr in the storage layer, and

a second state is stored in the memory element by applying a second voltage or a current pulse opposite in polarity to the first voltage or the current pulse between the first electrode and the second electrode to eliminate the conduction path formed in the storage layer.

8. The memory element of claim 1 , wherein the high-resistance layer is an oxide or a nitride.

9. A memory device comprising: a plurality of memory elements, each having a storage layer containing an ion source layer between a first electrode and a second electrode, the memory element storing information by changing an electrical characteristic of the storage layer; and pulse application means for selectively applying a voltage or current pulse to the plurality of memory elements, wherein at least Zr is added to the ion source layer as a metal element together with an ion conducting material, wherein the amount of Zr contained in the ion source layer 3 atom % or more, wherein the storage layer has a high-resistance layer higher in resistance value than the ion source layer between the ion layer and the first electrode.

10. The memory device of claim 9 wherein the amount of Zr contained in the ion source layer is from 3 atom % or more to 40 atom % or less.

11. The memory device of claim 9 , wherein the ion source layer further contains Cu.

12. The memory device of claim 11 , wherein the ion source layer further contains Si.

13. The memory device of claim 12 , wherein the amount of Si contained in the ion source layer is from 10 atom % or more to 45 atom % or less.

14. The memory device of claim 9 , wherein each of the memory elements stores binary or more multilevel states.

15. The memory device of claim 9 , wherein some of the layers making up each of the memory elements are commonly formed with the same layers in the plurality of memory elements adjacent to each other.

16. The memory device of claim 15 , wherein the common layers in the plurality of memory elements are a high-resistance layer, ion source layer and second electrode, and the first electrode is formed separately for each of the memory elements.

17. The memory device of claim 9 , wherein

a first state is stored in the memory element by applying a first voltage or a current pulse between the first electrode and the second electrode to form a conduction path containing at least the Zr in the storage layer, and

a second state is stored in the memory element by applying a second voltage or a current pulse opposite in polarity to the first voltage or the current pulse between the first electrode and the second electrode to eliminate the conduction path formed in the storage layer.

18. The memory device of claim 9 , wherein the high-resistance layer is an oxide or a nitride.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 19, 2016
From: SONY CORPORATION
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 040419/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE THIRD INVETOR'S (TAKEYUKI SONE) EXECUATION DATE FROM 7/22/2008 TO 7/15/2008 PREVIOUSLY RECORDED ON REEL 021368 FRAME 0533. ASSIGNOR(S) HEREBY CONFIRMS THE THE EXECUTION DATE SHOULD READ 7/15/2008, NOT 7/22/2008. Recorded Aug 27, 2008
From: OHBA, KAZUHIRO; MIZUGUCHI, TETSUYA; SONE, TAKEYUKI; ENDO, KEITARO
To: SONY CORPORATION
Reel/Frame 021452/0175 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 11, 2008
From: OHBA, KAZUHIRO; MIZUGUCHI, TETSUYA; SONE, TAKEYUKI; ENDO, KEITARO
To: SONY CORPORATION
Reel/Frame 021368/0533 →