Semiconductor memory device
View Patent ↗In a two-transistor gain cell structure, a semiconductor memory device capable of stable reading without malfunction and having small-area memory cells is provided. In a two-transistor gain cell memory having a write transistor and a read transistor, a write word line, a read word line, a write bit line, and a read bit line are separately provided, and voltages to be applied are independently set. Furthermore, a memory cell is connected to the same read word line and write bit line as those of an adjacent memory cell.
1. A semiconductor memory device comprising:
a plurality of memory cells each including a first transistor and a second transistor, a gate electrode of the first transistor being connected to a source electrode of the second transistor,
wherein two memory cells of the plurality, which are arranged adjacent to each other, have a line-symmetric shape with respect to a boundary of the two memory cells,
wherein the second transistor is a thin film transistor,
wherein a source region, a drain region, and a channel region of the first transistor are formed in a semiconductor substrate, and
wherein a source region, a drain region, and a channel region of the second transistor are formed over the semiconductor substrate, through an insulating film.
2. A semiconductor memory device according to claim 1 , wherein the source region of the second transistor is a gate electrode of the first transistor.
3. A semiconductor memory device comprising:
a plurality of memory cells each including a first transistor and a second transistor, a gate electrode of the first transistor being connected to a source electrode of the second transistor,
wherein two memory cells of the plurality, which are arranged adjacent to each other, have a line-symmetric shape with respect to a boundary of the two memory cells,
wherein drain regions of second transistors of two of the memory cells, which are adjacently arranged in a first direction, are connected to each other, and
wherein drain regions of two of the second transistors of two of the memory cells, which are adjacently arranged in a second direction perpendicular to the first direction, are separated from each other.
4. A semiconductor memory device comprising:
a plurality of memory cells each including a first transistor and a second transistor, a gate electrode of the first transistor being connected to a source electrode of the second transistor,
wherein two memory cells of the plurality, which are arranged adjacent to each other, have a line-symmetric shape with respect to a boundary of the two memory cells, and
wherein second transistors of two of the memory cells, which are adjacently arranged in a second direction, are formed between first transistors of the two memory cells.
5. A semiconductor memory device according to claim 4 ,
wherein the first transistors of the memory cells are arranged in a row in a first direction perpendicular to the second direction, and
wherein the second transistors of the memory cells are arranged in a row in the first direction.
6. A semiconductor memory device according to claim 1 , wherein a thickness of the channel region of the second transistor is no more than 5 nm.