Encoding low density parity check (LDPC) codes through an LDPC decoder
An approach is providing for supporting broadcast transmission of low density parity check (LDPC) coded signals. A receiver includes a decoder configured to decode an LDPC signal to output a decoded signal. The decoder is further configured to operate as an encoder; as such, interference cancellation can be implemented by the encoder re-encoded the received decoded signal. The above approach has particular applicability to satellite broadcast systems.
1. A method comprising:
receiving a plurality of information bits that are to be encoded;
constructing a receiving vector based on the information bits;
initializing a low density parity check (LDPC) decoder with the constructed vector;
computing, by the decoder, d i =g(e 1,i ,e 2,i , . . . e v i −1 ) for an i-th check node, where v i is the number of edges connected to the i-th check node, e v i being an edge connected to a bit node corresponding to a non-information bit;
performing, by the decoder, a hard decision into a binary vector; and
computing a final parity check to output an encoded signal based on the binary vector.
2. A method according to claim 1 , wherein the hard decision is represented as d =(d 0 , . . . ,d n−k−1 ), and the binary vector is represented as b =(b 0 , . . . ,b n−k−1 ), the final parity check, p , being determined based on
p
i
=
∑
m
=
0
i
⊕
b
m
.
3. A method according to claim 1 , wherein a portion of the information bits is initialized either as a null value or a positive value associated with a maximum value of likelihood ratio for a channel bit.
4. A method according to claim 1 , wherein the encoded signal is used for interference cancellation with a received LDPC signal.
5. An apparatus comprising:
a low density parity check (LDPC) decoding logic configured to receive a plurality of information bits that are to be encoded, and to construct a receiving vector based on the information bits to initialize the decoding logic, wherein the decoding logic is further configured to compute d i =g(e 1,i ,e 2,i , . . . e v i −1 ) for an i-th check node, where v i is the number of edges connected to the i-th check node, e v i being an edge connected to a bit node corresponding to a non-information bit, and wherein the decoding logic is further configured to perform a hard decision into a binary vector and to compute a final parity check for outputting an encoded signal based on the binary vector.
6. An apparatus according to claim 5 , wherein the hard decision is represented as d =(d 0 , . . . ,d n−k−1 ), and the binary vector is represented as b =(b 0 , . . . ,b n−k−1 ), the final parity check, p , being determined based on
p
i
=
∑
m
=
0
i
⊕
b
m
.
7. An apparatus according to claim 5 , wherein a portion of the information bits is initialized either as a null value or a positive value associated with a maximum value of likelihood ratio for a channel bit.
8. An apparatus according to claim 5 , wherein the encoded signal is used for interference cancellation with a received LDPC signal.
9. A method comprising:
utilizing low density parity check (LDPC) decoding hardware to encode a plurality of information bits by:
constructing a receiving vector based on the information bits to initialize the decoding hardware,
computing, by the decoding hardware, d i =g(e 1,i ,e 2,i , . . . e v i −1 ) for an i-th check node, where v i is the number of edges connected to the i-th check node, e v i being an edge connected to a bit node corresponding to a non-information bit,
performing a hard decision into a binary vector, and
computing a final parity check to output an encoded signal based on the binary vector.
10. A method according to claim 9 , wherein the hard decision is represented as d =(d 0 , . . . d n−k−1 ), and the binary vector is represented as b =(b 0 , . . . ,b n−k−1 ), the final parity check, p , being determined based on
p
i
=
∑
m
=
0
i
⊕
b
m
.
11. A method according to claim 9 , wherein a portion of the information bits is initialized either as a null value or a positive value associated with a maximum value of likelihood ratio for a channel bit.
12. A method according to claim 9 , wherein the encoded signal is used for interference cancellation with a received LDPC signal.
13. A receiver comprising:
low density parity check (LDPC) decoding hardware configured to encode a plurality of information bits by:
constructing a receiving vector based on the information bits to initialize the decoding hardware,
computing d i =g(e 1,i ,e 2,i , . . . e v i −1 ) for an i-th check node, where v i is the number of edges connected to the i-th check node, e v i being an edge connected to a bit node corresponding to a non-information bit,
performing a hard decision into a binary vector, and
computing a final parity check to output an encoded signal based on the binary vector.
14. A receiver according to claim 13 , wherein the hard decision is represented as d =(d 0 , . . . ,d n−k−1 ), and the binary vector is represented as b =(b 0 , . . . ,b n−k−1 ), the final parity check, p , being determined based on
p
i
=
∑
m
=
0
i
⊕
b
m
.
15. A receiver according to claim 13 , wherein a portion of the information bits is initialized either as a null value or a positive value associated with a maximum value of likelihood ratio for a channel bit.
16. A receiver according to claim 13 , wherein the encoded signal is used for interference cancellation with a received LDPC signal.
17. A method comprising:
receiving a plurality of information bits that are to be encoded;
constructing a receiving vector based on the information bits;
initializing a low density parity check (LDPC) decoder with the constructed vector;
performing, by the decoder, a hard decision into a binary vector; and
computing a final parity check to output an encoded signal based on the binary vector;
wherein a portion of the information bits is initialized either as a null value or a positive value associated with a maximum value of likelihood ratio for a channel bit.
18. An apparatus comprising:
a low density parity check (LDPC) decoding logic configured to receive a plurality of information bits that are to be encoded, and to construct a receiving vector based on the information bits to initialize the decoding logic, wherein the decoding logic is further configured to perform a hard decision into a binary vector and to computer a final parity check for outputting an encoded signal based on the binary vector, and wherein a portion of the information bits is initialized either as a null value or a positive value associated with a maximum value of likelihood ratio for a channel bit.
19. A method comprising:
utilizing low density parity check (LDPC) decoding hardware to encode a plurality of information bits by,
constructing a receiving vector based on the information bits to initialize the decoding hardware,
performing a hard decision into a binary vector, and
computing a final parity check to output an encoded signal based on the binary vector,
wherein a portion of the information bits is initialized either as a null value or a positive value associated with a maximum value of likelihood ratio for a channel bit.
20. A receiver comprising:
low density parity check (LDPC) decoding hardware configured to encode a plurality of information bits by,
constructing a receiving vector based on the information bits to initialize the decoding hardware,
performing a hard decision into a binary vector, and
computing a final parity check to output an encoded signal based on the binary vector,
wherein a portion of the information bits is initialized either as a null value or a positive value associated with a maximum value of likelihood ratio for a channel bit.