IP Library Granted Patent US 7,912,064
Granted Patent B2
US 7,912,064 · App. 12/187,783 · Granted Mar 22, 2011

System and method for handling out-of-order frames

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,912,064
App. No.
12/187,783
Granted
Mar 22, 2011
Kind
B2
Abstract

A system for handling out-of-order frames may include one or more processors that enable receiving of an out-of-order frame via a network subsystem. The one or more processors may enable placing data of the out-of-order frame in a host memory, and managing information relating to one or more holes resulting from the out-of-order frame in a receive window. The one or more processors may enable setting a programmable limit with respect to a number of holes allowed in the receive window. The out-of-order frame is received via a TCP offload engine (TOE) of the network subsystem or a TCP-enabled Ethernet controller (TEEC) of the network subsystem. The network subsystem may not store the out-of-order frame on an onboard memory, and may not store one or more missing frames relating to the out-of-order frame. The network subsystem may include a network interface card (NIC).

Claims (63)

1. A system for handling out-of-order frames, comprising:

one or more processors that enable receiving of an out-of-order frame via a network subsystem;

said one or more processors enable placing data of the out-of-order frame in a host memory;

said one or more processors enable managing information relating to one or more holes resulting from the out-of-order frame in a receive window; and

said one or more processors enable setting a programmable limit with respect to a number of holes allowed in the receive window.

2. The system according to claim 1 , wherein the out-of-order frame is received via a TCP offload engine (TOE) of the network subsystem or a TCP-enabled Ethernet controller (TEEC) of the network subsystem.

3. The system according to claim 1 , wherein the network subsystem does not store the out-of-order frame on an onboard memory.

4. The system according to claim 3 , wherein the network subsystem does not store one or more missing frames relating to the out-of-order frame.

5. The system according to claim 1 , wherein the network subsystem comprises a network interface card (NIC).

6. The system according to claim 1 , wherein said one or more processors enable placing the data of the out-of-order frame in the host memory if the out-of-order frame is determined to be inside the receive window.

7. The system according to claim 1 , wherein said one or more processors enable dropping the out-of-order frame, if the out-of-order frame is determined not to be inside the receive window.

8. The system according to claim 1 , wherein said one or more processors enable placing a portion of the data of the out-of-order frame in the host memory, the portion of the data being inside the receive window.

9. The system according to claim 1 , wherein said one or more processors enable one or more of:

storing information relating to a new hole created by the placement of the data of the out-of-order frame,

updating information relating to an existing hole modified by the placement of the data of the out-of-order frame, and/or

deleting information relating to a plugged hole created by the placement of the data of the out-of-order frame.

10. The system according to claim 9 ,

wherein the stored information resides on the network subsystem,

wherein the updated information resides on the network subsystem, and

wherein the deleted information resided on the network subsystem.

11. The system according to claim 1 , wherein the managed information resides on the network subsystem.

12. The system according to claim 1 , wherein said one or more processors enable updating the receive window based upon the placement of the data of the out-of-order frame.

13. The system according to claim 1 , wherein said one or more processors enable mapping TCP space into host buffer space.

14. The system according to claim 1 , wherein the network subsystem comprises a memory whose memory usage scales with a number of holes in the receive window.

15. The system according to claim 1 , wherein the network subsystem comprises a memory whose memory usage does not scale with a number of out-of-order frames received.

16. A system for handling out-of-order frames, comprising:

one or more processors that enable receiving of an out-of-order frame via a network subsystem;

said one or more processors enable placing data of the out-of-order frame in a host memory; and

said one or more processors enable controlling a number of holes allowed in a received window utilized for handling said placed data.

17. The system according to claim 16 , wherein the out-of-order frame is received via a TCP offload engine (TOE) of the network subsystem or a TCP-enabled Ethernet controller (TEEC) of the network subsystem.

18. The system according to claim 16 , wherein the network subsystem does not store the out-of-order frame on an onboard memory.

19. The system according to claim 18 , wherein the network subsystem does not store one or more missing frames relating to the out-of-order frame.

20. The system according to claim 16 , wherein the network subsystem comprises a network interface card (NIC).

21. The system according to claim 16 , wherein said one or more processors enable placing the data of the out-of-order frame in the host memory if the out-of-order frame is determined to be inside the receive window.

22. The system according to claim 16 , wherein said one or more processors enable dropping the out-of-order frame, if the out-of-order frame is determined not to be inside the receive window.

23. The system according to claim 16 , wherein said one or more processors enable placing a portion of the data of the out-of-order frame in the host memory, the portion of the data being inside the receive window.

24. The system according to claim 16 , wherein said one or more processors enable one or more of:

managing information relating to one or more holes resulting from the out-of-order frame in a receive window;

storing information relating to a new hole created by the placement of the data of the out-of-order frame,

updating information relating to an existing hole modified by the placement of the data of the out-of-order frame, and/or

deleting information relating to a plugged hole created by the placement of the data of the out-of-order frame.

25. The system according to claim 23 ,

wherein the stored information resides on the network subsystem,

wherein the updated information resides on the network subsystem, and

wherein the deleted information resided on the network subsystem.

26. The system according to claim 24 , wherein the managed information resides on the network subsystem.

27. The system according to claim 16 , wherein said one or more processors enable updating the receive window based upon the placement of the data of the out-of-order frame.

28. The system according to claim 16 , wherein said one or more processors enable mapping TCP space into host buffer space.

29. The system according to claim 16 , wherein the network subsystem comprises a memory whose memory usage scales with a number of holes in the receive window.

30. The system according to claim 16 , wherein the network subsystem comprises a memory whose memory usage does not scale with a number of out-of-order frames received.

31. A network interface card (NIC), comprising:

a receiver for receiving a packet sequence from a network; and

a processor operable to manage information relating to one or more holes in the packet sequence, wherein a hole occurs when a subsequent packet is received prior to a missing packet, wherein the processor is operable to set a programmable limit on the number of holes allowed in a receive window, wherein data corresponding to the subsequent packet is placed in a host memory prior to receiving the missing packet.

32. The NIC according to claim 31 , wherein the receiver comprises a TCP offload engine (TOE).

33. The NIC according to claim 31 , wherein the receiver comprises a TCP-enabled Ethernet controller (TEEC).

34. The NIC according to claim 31 , wherein the missing packet is an out-of-order packet, wherein data corresponding to the out-of-order packet is placed in the host memory if the out-of-order packet is determined to be inside the receive window.

35. The NIC according to claim 34 , wherein the out-of-order packet is a retransmission of a packet dropped by the network.

36. The NIC according to claim 31 , wherein the missing packet is dropped by the processor, if the missing packet is determined not to be inside the receive window.

37. The NIC according to claim 31 , wherein the processor is operable to store information relating to a new hole created by the placement of the data of the missing packet.

38. The NIC according to claim 31 , wherein the processor is operable to update information relating to an existing hole modified by the placement of the data of the missing packet.

39. The NIC according to claim 31 , wherein the processor is operable to delete information relating to a plugged hole created by the placement of the data of the missing packet.

40. The system according to claim 31 ,

wherein the information resides on a network subsystem.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE PROPERTY NUMBERS PREVIOUSLY RECORDED AT REEL: 47630 FRAME: 344. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 21, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0267 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER TO 9/5/2018 PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0687. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047630/0344 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0687 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →