NOR flash memory device and method for fabricating the same
View Patent ↗Embodiments of a NOR flash memory and method for fabricating the same are provided. Bit lines can be formed as self-aligned source and drain regions between adjacent first polysilicon patterns. Contacts for the source and drain regions can be provided according to bit line instead of per cell. Word lines can be formed as second polysilicon patterns, which are used as control gates, and are provided perpendicular to the longitudinal axis of the bit lines. During formation of the second polysilicon patterns, a dielectric film and exposed regions of the first polysilicon patterns can be etched to form floating gates below the second polysilicon patterns.
1. A NOR flash memory device comprising:
a gate on a semiconductor substrate, the gate comprising:
first polysilicon patterns spaced apart by a predetermined interval, and providing floating gates,
a dielectric film on the first polysilicon patterns, and
a second polysilicon pattern aligned over the first polysilicon patterns and on the dielectric film, and providing a control gate for the floating gates;
a plurality of electrodes in a line form, each electrode provided in the semiconductor substrate at the interval between adjacent first polysilicon patterns; and
contacts for the plurality of electrodes, the contacts provided at an end region on each electrode;
wherein the dielectric film comprises an oxide-nitride-oxide (ONO) film configured of a stack of a first oxide film, a nitride film, and a second oxide film,
wherein a portion of the first oxide film contacting the plurality of electrodes is thicker than a portion of the first oxide film contacting the first polysilicon patterns,
wherein the portion of the first oxide film contacting the plurality of electrodes has a thickness of about 250˜300 Å.
2. The NOR flash memory device according to claim 1 , wherein the second polysilicon pattern forms a word line.
3. The NOR flash memory device according to claim 1 , wherein each of the plurality of electrodes forms a bit line.
4. The NOR flash memory device according to claim 1 , wherein the plurality of electrodes are formed in an intersecting pattern with the second polysilicon pattern such that each electrode extends in a direction perpendicular to the longitudinal axis of the second polysilicon pattern.
5. The NOR flash memory device according to claim 1 , wherein the plurality of electrodes are self aligned between the adjacent first polysilicon patterns.
6. The NOR flash memory device according to claim 1 , wherein the plurality of electrodes are formed by implantation of ions into regions of the semiconductor substrate.