Active device array substrate and method for fabricating the same
An active device array substrate and its fabricating method are provided. According to the subject invention, the elements of an array substrate such as the thin film transistors, gate lines, gate pads, data lines, data pads and storage electrodes, are provided by forming a patterned first metal layer, an insulating layer, a patterned semiconductor layer and a patterned metal multilayer. Furthermore, the subject invention uses the means of selectively etching certain layers. Using the aforesaid means, the array substrate of the subject invention has some layers with under-cut structures, and thus, the number of the time-consuming and complicated mask etching process involved in the production of an array substrate can be reduced. The subject invention provides a relatively simple and time-saving method for producing an array substrate.
1. An active device array substrate, comprising:
a substrate;
a patterned first metal layer on the substrate, wherein the patterned first metal layer comprises a plurality of gate lines, a plurality of gates and a plurality of gate pads, and the gate lines are connected with the gates and the gate pads;
a patterned first insulating layer on the substrate and the patterned first metal layer;
a patterned semiconductor layer on the patterned first insulating layer;
a patterned metal multilayer, which includes a plurality of data lines, a plurality of drains, a plurality of storage electrodes, a plurality of sources and a plurality of data pads, wherein the data lines are connected with the sources and the data pads, the sources and the drains are respectively configured above the gates, each of the drains and each of the storage electrodes respectively have a drain opening and a storage electrode opening, and the drain openings and the storage electrode openings expose parts of the patterned semiconductor layer;
a patterned second insulating layer, parts of which are on the patterned metal multilayer, wherein the patterned second insulating layer and the patterned first insulating layer expose parts of the drain openings, parts of the storage electrode openings, parts of the data lines, parts of the data pads, parts of the gate lines, and parts of the gate pads, and wherein the exposed storage electrode openings and exposed drain openings have under-cut structures; and
a patterned conducting layer, which includes a plurality of pixel electrodes electrically connected to the drains individually.
2. The active device array substrate of claim 1 , wherein the patterned semiconductor layer is on the first insulating layer corresponding to the top of the gates, on parts of the first insulating layer corresponding to the underside of the drains, and on parts of the first insulating layer corresponding to the underside of the storage electrodes.
3. The active device array substrate of claim 1 , wherein the data lines and the data pads are on the first insulating layer, and the data lines intersect the gate lines.
4. The active device array substrate of claim 1 , wherein the patterned metal multilayer comprises a second metal layer and a third metal layer from top to bottom.
5. The active device array substrate of claim 4 , wherein the second metal layer is an aluminum layer, and the third metal layer is a titanium layer, a molybdenum layer, or an alloy layer thereof.
6. The active device array substrate of claim 4 , wherein the second metal layer has under-cut structures.
7. The active device array substrate of claim 1 , wherein the patterned first metal layer comprises an upper metal layer and a lower metal layer.
8. The active device array substrate of claim 7 , wherein the upper metal layer is an aluminum layer, and the lower metal layer is a titanium layer, a molybdenum layer, or an alloy layer thereof.
9. The active device array substrate of claim 7 , wherein the upper metal layer has under-cut structures.
10. The active device array substrate of claim 7 , wherein the positions of the storage electrodes partially overlap the positions of the gate lines as seen from top to bottom.
11. The active device array substrate of claim 1 , wherein the patterned first metal layer further comprises a plurality of common lines and a plurality of common pads connected with the common lines, wherein the positions of the storage electrodes partially overlap the positions of the common lines as seen from top to bottom.