Semiconductor device
View Patent ↗In order to suppress an off leak current of an off transistor for ESD protection, in an NMOS for ESD protection whose isolation region has a shallow trench structure, a drain region is placed apart from the shallow trench isolation region so as not to be in direct contact with the shallow trench isolation region in a region where the drain region of the NMOS transistor for ESD protection is adjacent to at least a gate electrode of the NMOS transistor for ESD protection.
1. A semiconductor device comprising an n-type metal oxide semiconductor transistor for electrostatic discharge protection, the n-type metal oxide semiconductor transistor comprising:
a semiconductor substrate;
a shallow trench isolation region disposed on the semiconductor substrate to define a perimeter of an area for the n-type metal oxide semiconductor transistor, the shallow trench isolation region comprising a first portion and a second portion laterally adjacent to the first portion; and
a gate electrode, a source region and a drain region, wherein at least a portion of the gate electrode overlaps the first portion of the shallow trench isolation region, and wherein a first portion of an outer edge of the drain region is separated from the second portion of the shallow trench isolation and a second portion of the outer edge of the drain region abuts with the shallow trench isolation region, and wherein a distance between the first portion of the outer edge of the drain region and the second portion of the shallow trench isolation region adjacent to the first portion of the shallow trench isolation region overlapped by the gate electrode is equal to or greater than a gate length of the n-type metal oxide semiconductor transistor,
wherein the source region abuts with the shallow trench isolation region.