Semiconductor device
View Patent ↗Provided is a semiconductor device including an n-type metal oxide semiconductor transistor for electrostatic discharge protection including drain regions connected with a first metal interconnect and source regions connected with another first metal interconnect alternately placed with each other, and gate electrodes each placed between each of the drain regions and each of the source regions, in which: at least one of the first metal interconnect and the other first metal interconnect being connected to a plurality of layers of metal interconnects other than the first metal interconnect; and the source regions include via-holes for electrically connecting the other first metal interconnect and the plurality of layers of metal interconnects other than the first metal interconnect, a greater number of the via-holes is formed as a distance of an interconnect connected to the NMOS transistor for ESD protection becomes larger.
1. A semiconductor device comprising:
an n-type metal oxide semiconductor transistor for electrostatic discharge protection having a structure in which a plurality of transistors is integrated, and comprising a plurality of drain regions electrically connected to an external connection terminal, a plurality of source regions electrically connected to a ground potential supply line alternately placed with each other, and a plurality of gate electrodes each placed between each of the plurality of drain regions and each of the plurality of source regions,
wherein the plurality of drain regions are connected with a first metal interconnect, and the plurality of source regions are connected with another first metal interconnect, at least one of the first metal interconnect and the another first metal interconnect being connected to a plurality of layers of metal interconnects other than the first metal interconnect and the another first metal interconnect; and
wherein the plurality of source regions include via-holes for electrically connecting the another first metal interconnect and the plurality of layers of metal interconnects other than the first metal interconnect and the another first metal interconnect, a greater number of the via-holes being formed as a distance of an interconnect connected to the n-type metal oxide semiconductor transistor for electrostatic discharge protection from outside becomes larger.
2. A semiconductor device according to claim 1 :
wherein the plurality of layers of metal interconnects other than the first metal interconnect and the another first metal interconnect are lined in a direction perpendicular to a channel width direction of the n-type metal oxide semiconductor transistor for electrostatic discharge protection;
wherein the first metal interconnect is placed in a direction parallel to the channel width direction of the n-type metal oxide semiconductor transistor for electrostatic discharge protection; and
wherein the plurality of layers of metal interconnects other than the first metal interconnect and the another first metal interconnect are connected to the first metal interconnect and the another first metal interconnect via the via-holes on one of the plurality of drain regions and the plurality of source regions.
3. A semiconductor device according to claim 2 , wherein the via-holes are placed to be widely distributed in the direction parallel to the channel width direction of the n-type metal oxide semiconductor transistor for electrostatic discharge protection on one of the plurality of drain regions and the plurality of source regions.
4. A semiconductor device according to claim 2 , wherein the via-holes are placed to be concentrated on one of a part of each of the plurality of drain regions and a part of each of the plurality of source regions.
5. A semiconductor device according to claim 1 , wherein the first metal interconnect, the another first metal interconnect, and the plurality of layers of metal interconnects other than the first metal interconnect and the another first metal interconnect include a refractory metal.