INTERLEAVED SLAVE SWITCHING CIRCUIT FOR DISCONTINUOUS MODE PFC CONVERTER
A slave switching circuit for a master-slave PFC converter is disclosed. The slave switching circuit includes a phase-detection circuit coupled to detect a master-switching signal and a slave-inductor signal for generating a start signal and a phase-lock signal. The start signal is coupled to enable a slave-switching signal. The slave-switching signal is coupled to switch a slave inductor. An on-time-adjust circuit is used to adjust the on-time of the slave-switching signal in accordance with the phase-lock signal. The slave-inductor signal is correlated to the demagnetization of the slave inductor. The phase-lock signal is coupled to minimize the period between the disablement of the slave-inductor signal and the enablement of the start signal.
1 . A slave switching circuit for a master-slave power factor correction (PFC) converter, the slave switching circuit comprising:
a phase-detection circuit, coupled to detect a master-switching signal and a slave-inductor signal for generating a start signal and a phase-lock signal, wherein the start signal is utilized to enable a slave-switching signal, and the slave-switching signal is coupled to switch a slave inductor; and
an on-time-adjust circuit, coupled to adjust the on-time of the slave-switching signal in accordance with the phase-lock signal,
wherein the slave-inductor signal is correlated to the demagnetization of the slave inductor, and the phase-lock signal is coupled to minimize the period between the disablement of the slave-inductor signal and the enablement of the start signal.
2 . The slave switching circuit as claimed in claim 1 , further comprising:
a power management circuit, coupled to receive the master-switching signal for decreasing the on-time of the slave-switching signal when the on-time of the master-switching signal is decreased and its pulse width is lower than a threshold.
3 . The slave switching circuit as claimed in claim 1 , wherein the slave-switching signal is turned off before the enablement of the start signal, which determines the maximum duty cycle of the slave-switching signal.
4 . The slave switching circuit as claimed in claim 1 , wherein the start signal is generated in accordance with a switching period of the master-switching signal.
5 . The slave switching circuit as claimed in claim 1 , wherein the on-time-adjust circuit is developed to adjust the on-time of the slave-switching signal for minimizing the period between the disablement of the slave-inductor signal and the enablement of the start signal.
6 . The slave switching circuit as claimed in claim 1 , wherein the phase-detection circuit comprises:
a phase-signal generator, generating the start signal in accordance with a switching period of the master-switching signal; and
a lock-signal generator, generating the phase-lock signal in response to the slave-inductor signal and the slave-switching signal,
wherein the start signal is generated after a phase shift of the master-switching signal, and the phase-lock signal is produced in accordance with the period between the disablement of the slave-inductor signal and the enablement of the slave-switching signal.
7 . The slave switching circuit as claimed in claim 1 , wherein the on-time-adjust circuit comprises:
a flip-flop, coupled to enable the slave-switching signal in response to the start signal;
a ramp-signal generator, generating a ramp signal in response to the slave-switching signal;
an up/down counter, coupled to the phase-lock signal to generate a digital code;
a digital-to-analog converter, producing an analog signal in accordance with the digital code; and
a comparator, coupled to disable the slave-switching signal in response to the comparison of the analog signal and the ramp signal.
8 . A method for providing an interleaved slave switching circuit for a master-slave PFC converter, the method comprising:
generating a slave-switching signal in response to a phase-lock signal, the slave-switching signal being coupled to switch a slave inductor; and
generating the phase-lock signal in accordance with a slave-inductor signal and the slave-switching signal, the phase-lock signal being coupled to control the on-time of the slave-switching signal,
wherein the slave-inductor signal is correlated to the demagnetization of the slave inductor, and the slave inductor is connected with a master inductor in parallel to the output of the PFC converter.
9 . The method as claimed in claim 8 , further comprising:
generating a start signal in accordance with a master-switching signal, the start signal being coupled to enable the slave-switching signal,
wherein the start signal is generated after a phase shift of the master-switching signal.
10 . The method as claimed in claim 8 , wherein the phase-lock signal is utilized to adjust the on-time of the slave-switching signal for minimizing the period between the disablement of the slave-inductor signal and the enablement of the slave-switching signal.
11 . The method as claimed in claim 8 , further comprising:
decreasing the on-time of the slave-switching signal in response to the on-time of the master-switching signal,
wherein the on-time of the slave-switching signal is decreased when the on-time of the master-switching signal is decreased and its pulse width is lower than a threshold.