IP Library Granted Patent US 9,195,628
Granted Patent B2
US 9,195,628 · App. 12/192,160 · Granted Nov 24, 2015

Partitioned bluetooth system

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Quick Facts
Patent No.
US 9,195,628
App. No.
12/192,160
Granted
Nov 24, 2015
Kind
B2
Abstract

A system includes a first memory, a second memory, a host processor, and a second processor. The first memory is configured to store first layers of a Bluetooth protocol stack including at least a portion of a link manager layer. The second memory is configured to store second layers of the Bluetooth protocol stack. The second layers have higher real-time requirements than the first layers. The host processor is coupled to the first memory. The host processor is configured to execute the first layers. The second processor is coupled to the second memory. The second processor is configured to execute the second layers.

Claims (14)

1. A system comprising:

a first memory configured to store first layers of a Bluetooth protocol stack including at least a portion of a link manager layer;

a second memory configured to store second layers of the Bluetooth protocol stack, the second layers having higher real-time requirements than the first layers;

a host processor coupled to the first memory, the host processor configured to execute the first layers;

and a second processor coupled to the second memory, the second processor configured to execute the second layers, wherein the first memory and the second memory exclude a Bluetooth specified transport layer of the Bluetooth protocol stack.

2. The system of claim 1 , wherein the first memory and the host processor are on different chips.

3. The system of claim 1 , wherein the second memory and the second processor are on a single chip.

4. The system of claim 1 , wherein the second memory, the host processor, and the second processor are on a single chip.

5. The system of claim 1 , wherein the first layers comprise at least a portion of a host controller interface command and event handler layer.

6. The system of claim 1 , wherein the second layers comprise at least a portion of a link controller layer and at least a portion of a baseband firmware layer.

7. The system of claim 1 , further comprising:

a third memory coupled to the host processor, the third memory configured to store payload buffers.

8. The system of claim 7 , further comprising:

a fourth memory coupled to the second processor, the fourth memory configured to store payload buffers.

Assignments (9)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 17, 2020
From: INTEL CORPORATION
To: APPLE INC.
Reel/Frame 053518/0586 →
CONFIRMATORY ASSIGNMENT EFFECTIVE AS OF JANUARY 1, 2018 Recorded Aug 12, 2020
From: INTEL DEUTSCHLAND GMBH
To: INTEL CORPORATION
Reel/Frame 053477/0001 →
CHANGE OF NAME Recorded Nov 6, 2015
From: INTEL MOBILE COMMUNICATIONS GMBH
To: INTEL DEUTSCHLAND GMBH
Reel/Frame 037057/0061 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 19, 2012
From: INTEL MOBILE COMMUNICATIONS TECHNOLOGY GMBH
To: INTEL MOBILE COMMUNICATIONS GMBH
Reel/Frame 027556/0709 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 18, 2012
From: INFINEON TECHNOLOGIES AG
To: INTEL MOBILE COMMUNICATIONS TECHNOLOGY GMBH
Reel/Frame 027548/0623 →
CORRECTED ASSIGNMENT CORRECTING SPELLING OF CONVEYOR'S LAST NAME REEL 022332/FRAME 0159 Recorded Mar 5, 2009
From: OESTERGREN, JOHAN; LEWIS, MICHAEL
To: INFINEON TECHNOLOGIES AG
Reel/Frame 022349/0859 →
CORRECTED ASSIGNMENT CORRECTING SPELLING OF CONVEYOR'S LAST NAME REEL 021393/FRAME 0585 Recorded Mar 5, 2009
From: OESTERGREN, JOHAN; LEWIS, MICHAEL
To: INFINEON TECHNOLOGIES AG
Reel/Frame 022351/0625 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 27, 2009
From: OSTERGREN, JOHAN; LEWIS, MICHAEL
To: INFINEON TECHNOLOGIES AG
Reel/Frame 022332/0159 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 15, 2008
From: OSTERGREN, JOHAN; LEWIS, MICHAEL
To: INFINEON TECHNOLOGIES AG
Reel/Frame 021393/0585 →