IP Library Granted Patent US 8,135,029
Granted Patent B1
US 8,135,029 · App. 12/192,318 · Granted Mar 13, 2012

Method and apparatus for a high-speed frame tagger

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,135,029
App. No.
12/192,318
Granted
Mar 13, 2012
Kind
B1
Abstract

A method is described including extracting protocol information from a received packet within a framer, comparing the protocol information in a first pass to predetermined values to produce a first result, and tagging the packet based on the set of results.

Claims (29)

1. A method, comprising:

extracting protocol information from a received packet within a framer;

comparing the protocol information in a first pass to predetermined values to produce a first result;

and tagging the packet based on the first result if the first result is negative;

the method further comprising comparing the protocol information in a second pass to predetermined values, if the first result is positive, to produce a second result, wherein the first and second results form a set of results.

2. The method of claim 1 , further comprising comparing the protocol information in a third pass to predetermined values to produce a third result of the set of results.

3. The method of claim 1 , further comprising tagging the set of results.

4. An apparatus, comprising:

a network processor interface;

a central processor interface;

a protocol determination logic block to determine a protocol type of data in a packet, wherein the protocol determination logic block compares protocol information of the packet in a first pass to predetermined values to produce a first result; and

a tag select logic block to apply a tag to the packet indicating that the packet should be sent to either the central processor interface or the network processor interface based on the first result, if the first result is negative.

5. The apparatus of claim 4 , wherein the protocol determination logic block includes a data register to store the protocol information of the packet.

6. The apparatus of claim 5 , wherein the protocol determination logic block includes a comparator to compare contents of the data register to the predetermined values.

7. The apparatus of claim 6 , wherein the protocol determination logic block includes a tag selector to select a tag based on the first result.

8. The apparatus of claim 7 , wherein the protocol determination logic block includes a protocol code memory to store the predetermined values.

9. The apparatus of claim 8 , wherein the network processor interface, central processor interface, and protocol determination logic block reside in a framer.

10. The apparatus of claim 9 , further comprising a central processor coupled to the central processor interface of the framer.

11. The apparatus of claim 10 , further comprising a network processor coupled to the network processor interface of the framer.

12. The apparatus of claim 11 , further comprising a physical link layer coupled to the framer.

13. The apparatus of claim 12 further comprising a software stack coupled to the framer.

14. The apparatus of claim 13 further comprising a host system coupled to the software stack and the network processor.

15. The apparatus of claim 4 , wherein the protocol determination logic block compares protocol information of the packet in a second pass to predetermined values to produce a second result, the first result and second result forming a set of results, and the tag select logic block to apply a tag to the packet based on set of results.

16. An apparatus, comprising:

means for extracting protocol information from a received packet within a framer;

means for comparing the protocol information in a first pass to predetermined values to produce a first result; and

means for tagging tile packet based on the first result if the first result is negative;

the method further comprising means for comparing the protocol information in a second pass to predetermined values, if the first result is positive, to produce a second result, wherein the first and second results form a set of results.

17. The method of claim 16 , further comprising means for comparing the protocol information in a third pass to predetermined values to produce a third result of the set of results.

Assignments (9)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 21, 2023
From: INTELLECTUAL VENTURES ASSETS 162 LLC
To: WINTERSPRING IP LLC
Reel/Frame 064646/0876 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 21, 2023
From: WINTERSPRING IP LLC
To: WINTERSPRING DIGITAL LLC
Reel/Frame 064647/0045 →
SECURITY INTEREST Recorded Jul 21, 2021
From: WINTERSPRING IP LLC
To: INTELLECTUAL VENTURES ASSETS 169 LLC; INTELLECTUAL VENTURES ASSETS 162 LLC
Reel/Frame 056932/0665 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 11, 2021
From: CHEMTRON RESEARCH LLC
To: INTELLECTUAL VENTURES ASSETS 162 LLC
Reel/Frame 056514/0724 →
MERGER Recorded Oct 9, 2015
From: RUCTION CAPITAL LIMITED LIABILITY COMPANY
To: CHEMTRON RESEARCH LLC
Reel/Frame 036765/0929 →
CORRECTIVE ASSIGNMENT TO CORRECT THE STATE OF INCORPORATION SET FORTH ON THE ASSIGNMENT FROM <CALIFORNIA> TO <DELAWARE>, PREVIOUSLY RECORDED ON REEL 027780 FRAME 0598. ASSIGNOR(S) HEREBY CONFIRMS THE SALE, ASSIGNMENT, AND TRANSFER OF APPLICATION NO. 12/192,318 (NOW PATENT NO. 8,135,029) TO CYPRESS SEMICONDUCTOR CORPORATION. Recorded Apr 13, 2012
From: VASUDEVAN, VELAMUR KRISHNAMACHARI; ANNAYYA, DINESH
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 028042/0499 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 23, 2012
From: CYPRESS SEMICONDUCTOR CORPORATION
To: RUCTION CAPITAL LIMITED LIABILITY COMPANY
Reel/Frame 027921/0579 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 29, 2012
From: VASUDEVAN, VELAMUR KRISHNAMACHARI; ANNAYYA, DINESH
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 027780/0598 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 28, 2012
From: WANG, YUN-CHE; SHAH, GAURANG
To: CYPRESS SEMICONDUCTOR
Reel/Frame 027778/0454 →