Semiconductor device
View Patent ↗Provided is a semiconductor device including an electrostatic discharge (ESD) protection element provided between an external connection terminal and an internal circuit region. In the semiconductor device, interconnect extending from the external connection terminal to the ESD protection element includes a plurality of metal interconnect layers so that a resistance of the interconnect extending from the external connection terminal to the ESD protection element is made smaller than a resistance of interconnect extending from the ESD protection element to an internal element. The interconnect extending from the ESD protection element to the internal element includes metal interconnect layers equal to or smaller in number than the plurality of interconnect layers used in the interconnect extending from the external connection terminal to the ESD protection element.
1. A semiconductor device, comprising:
an electrostatic discharge protection transistor disposed between an external connection terminal and an internal element and receiving electrostatic discharge surge and releasing a current through a bipolar operation, in order to protect the internal element from breakdown due to electrostatic discharge;
a first interconnect structure extending from the external connection terminal to the electrostatic discharge protection transistor and comprising a plurality of metal interconnect layers which are electrically coupled to a drain region of the electrostatic discharge protection transistor; and
a second interconnect structure arranged between the electrostatic discharge protection transistor and the internal element;
wherein a resistance across the first interconnect structure is smaller than the resistance across the second interconnect structure such that the electrostatic discharge surge is drawn to the electrostatic discharge protection transistor.
2. A semiconductor device according to claim 1 , wherein the electrostatic discharge protection transistor comprises an electrostatic discharge protection NMOS transistor in which a gate potential is fixed to a ground potential.
3. A semiconductor device according to claim 1 , wherein the drain of the electrostatic discharge protection transistor is coupled to the plurality of metal interconnect layers via multiple contact holes distributed across the entire drain.
4. A semiconductor device according to claim 1 , wherein only the first interconnect structure comprises the plurality of metal interconnect layers.
5. A semiconductor device according to claim 1 , wherein the first interconnect structure and the second interconnect structure comprise a metal interconnect layer made from a refractory metal.
6. A semiconductor device according to claim 2 ,
wherein the electrostatic discharge protection NMOS transistor comprises a drain region in which the plurality of metal interconnect layers are arranged over an entire surface of the drain region, and the drain region and the plurality of metal interconnect layers are electrically connected to each other via a contact hole and a via-hole.
7. A semiconductor device, comprising:
an electrostatic discharge protection element disposed between an external connection terminal and an internal element in order to protect the internal element from breakdown due to electrostatic discharge;
a first interconnect structure extending from the external connection terminal to the electrostatic discharge protection element; and
a second interconnect structure extending from the electrostatic discharge protection element to the internal element;
wherein the first interconnect structure shares at least one metal layer with the second interconnect structure;
wherein a resistance across the first interconnect structure is smaller than the resistance across the second interconnect structure such that the electrostatic discharge surge is drawn to the electrostatic discharge protection element.