IP Library Patent Application 12192894
Patent Application
App. No. 12/192,894

MULTIPLE TASK MANAGEMENT BETWEEN PROCESSORS

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Quick Facts
Patent No.
US None
App. No.
12/192,894
Abstract

A system for multiple task management between processors includes a first processing device for executing tasks. A respective storage element is provided for storing one or more commands from each of the tasks. A command dispatcher is provided for selectively transferring a command from one of the storage elements to a command queue provided within a second processing device.

Claims (34)

1 . A system comprising:

a first processing device to execute a plurality of tasks;

a plurality of storage elements, each provided to store one or more commands from a respective one of the plurality of tasks;

a second processing device including a command queue; and

a command dispatcher to selectively transfer a command from one of the plurality of storage elements to the command queue.

2 . The system of claim 1 wherein the command dispatcher is configured to transfer the command from one of the plurality of storage elements to the command queue when the command queue is not full.

3 . The system of claim 1 wherein the command dispatcher is implemented in software.

4 . The system of claim 3 wherein the command dispatcher is configured to transfer a command from one of the plurality of storage elements to the command queue in response to an interrupt generated by the second processing device.

5 . The system of claim 4 wherein the second processing device is configured to generate the interrupt when the command queue is not full.

6 . The system of claim 1 wherein the command dispatcher is implemented in hardware.

7 . The system of claim 6 wherein the storage element comprises a first-in first-out (FIFO) memory register.

8 . The system of claim 7 wherein the command dispatcher comprises logic circuitry to transfer the commands from the FIFO memory register to the command queue.

9 . The system of claim 1 further comprising a compiler to mark a first set of points in at least one of the plurality of tasks for saving a state associated with the task.

10 . The system of claim 9 wherein the compiler is configured to mark a second set of points in at least one of the plurality of tasks for restoring a state associated with the task.

11 . The system of claim 1 further comprising a multiple-bank storage element for storing a state associated with each of the plurality of tasks.

12 . The system of claim 11 wherein the second processing device comprises circuitry to store the state associated with a first task of the plurality of tasks and to load, concurrently, the state associated with a second task of the plurality of tasks.

13 . A method of operation within a first processing device, the method comprising:

executing a plurality of tasks;

storing one or more commands from each of the plurality of tasks; and

selectively transferring the one or more commands to a second processing device based, at least in part, on the fullness of a command queue of the co-processing device.

14 . The method of claim 13 wherein selectively transferring the one or more commands comprises transferring each of the one or more commands while the command queue is not full.

15 . The method of claim 14 further comprising receiving an interrupt from the second processing device indicating that the command queue not full.

16 . The method of claim 13 wherein storing one or more commands comprises storing the one or more commands from each of the plurality of tasks in respective first-in-first-out (FIFO) memory registers.

17 . The method of claim 13 further comprising marking a first set of points in at least one of the plurality of tasks for saving a state associated with the task.

18 . The method of claim 17 further comprising marking a second set of points in at least one of the plurality of tasks for restoring a state associated with the task.

19 . A processing device comprising:

means for executing a plurality of tasks;

means for storing one or more commands from each of the plurality of tasks; and

means for selectively transferring the one or more commands to a second processing device based, at least in part, on the fullness of a command queue of the co-processing device.

20 . Computer-readable storage media comprising instructions which, when executed by the processor of a data processing device, result in inputting a netlist description of a processing system, the netlist description including:

a first processing device to execute a plurality of tasks;

a plurality of storage elements, each provided to store one or more commands from a respective one of the plurality of tasks;

a second processing device including a command queue; and

a command dispatcher to selectively transfer a command from one of the plurality of storage elements to the command queue.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 5, 2011
From: MATTSON, PETER; SOUTHGATE, TIMOTHY J.; KHAILANY, BRUCEK; RYGH, MARK; LIN, JIM JIAN; RAO, RAGHUNATH; HESKY, KENNETH; UEBEL, UDO
To: STREAM PROCESSORS, INC.
Reel/Frame 026709/0049 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 4, 2011
From: THE SKEET PRACTICE, LLC
To: CALOS FUND LIMITED LIABILITY COMPANY
Reel/Frame 026701/0037 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 4, 2011
From: DYNACOLOR, INC.
To: STREAM DEVELOPMENT CORPORATION
Reel/Frame 026704/0387 →
PEACEFUL FORECLOSURE AGREEMENT AND BILL OF FORECLOSURE SALE Recorded Aug 4, 2011
From: STREAM PROCESSORS, INC.
To: DYNACOLOR INC.
Reel/Frame 026704/0721 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 4, 2011
From: STREAM DEVELOPMENT CORPORATION
To: THE SKEET PRACTICE, LLC
Reel/Frame 026704/0433 →
RELEASE OF SECURITY INTEREST Recorded May 26, 2011
From: PINNACLE VENTURES, L.L.C.
To: DYNACOLOR, INC.
Reel/Frame 026344/0966 →
SECURITY AGREEMENT Recorded Mar 26, 2009
From: STREAM PROCESSORS, INC.
To: PINNACLE VENTURES, L.L.C., AS AGENT
Reel/Frame 022458/0488 →