Systems, methods, and apparatus for controlling the elements of superconducting processors
View Patent ↗A computer system employs a network that between a data programming system and one or more superconducting programmable devices of a superconducting processor chip. Routers on the network, such as first-, second- and third-stage routers direct communications with the superconducting programmable devices. A superconducting memory register may load data signals received from a first-stage router into corresponding superconducting programmable devices. The system may employ additional superconducting chips, first-, second- or third-stage routers.
1. A computer system comprising:
a first superconducting processor chip that includes a first set of superconducting programmable devices;
a data programming system for establishing data signals wherein a data signal includes programming information for at least one superconducting programmable device and routing information that identifies to which superconducting programmable device the data signal corresponds;
a communication network that establishes a communication path between the data programming system and at least one of the superconducting programmable device from the first set of superconducting programmable devices; and
a first first-stage router that interrupts the communication path between the data programming system and the at least one superconducting programmable device from the first set of superconducting programmable devices.
2. The computer system of claim 1 wherein the superconducting processor chip includes a superconducting quantum processor and at least one of the superconducting programmable devices is selected from the group consisting of: a superconducting flux qubit, a superconducting phase qubit, a superconducting charge qubit, a superconducting hybrid qubit, a superconducting memory register, a single flux quantum shift register, a quantum flux parametron device, and a superconducting coupling device.
3. The computer system of claim 1 wherein the communication path between the first first-stage router and the at least one superconducting programmable device is interrupted by a superconducting memory register which receives a data signal from the first first-stage router and loads the data signal into the corresponding superconducting programmable device.
4. The computer system of claim 3 wherein at least one superconducting memory register is selected from the group consisting of: a single flux quantum shift register, a flux-based shift register comprising latching qubits, and a quantum flux parametron shift register.
5. The computer system of claim 1 wherein the first first-stage router is a superconducting packet router.
6. The computer system of claim 5 wherein the first first-stage router is integrated on the first superconducting processor chip and communication paths between the first first-stage router and the first set of superconducting programmable devices are superconducting.
7. The computer system of claim 1 , further comprising:
a second superconducting processor chip that includes a second set of superconducting programmable devices;
at least one additional communication path that establishes communication between the data programming system and at least one of the superconducting programmable devices from the second set of superconducting programmable devices; and
a second first-stage router that interrupts the communication path between the data programming system and the at least one superconducting programmable device from the second set of superconducting programmable devices.
8. The computer system of claim 7 , further comprising a first second-stage router that interrupts the communication paths between the data programming system and the first and the second first-stage routers.
9. The computer system of claim 8 wherein the first second-stage router is a superconducting packet router and the communication paths between the first second-stage router and each of the first and the second first-stage routers are superconducting.
10. The computer system of claim 8 wherein the first second-stage router is an optical router and at least one communication path between the data programming system and the first second-stage router and at least one of the communication paths between the first second-stage router and each of the first and the second first-stage routers are optical signal paths.
11. The computer system of claim 8 wherein the first and the second superconducting processor chips are both disposed on a first base plate.
12. The computer system of claim 11 wherein the first and the second first-stage routers are both disposed on the first base plate.
13. The computer system of claim 11 wherein the first base plate includes a superconducting multi-chip module and at least a portion of communication on the first base plate is through superconducting traces.
14. The computer system of claim 11 wherein the first base plate is circular in geometry.
15. The computer system of claim 11 wherein the first second-stage router is also disposed on the first base plate.
16. The computer system of claim 11 , further comprising:
a second base plate upon which is disposed at least one superconducting processor chip that includes an additional set of superconducting programmable devices;
at least one additional communication path that establishes communication between the data programming system and at least one superconducting programmable device on the second base plate;
at least one additional first-stage router that interrupts a communication path between the data programming system and at least one superconducting programmable device on the second base plate; and
a second second-stage router that interrupts a communication path between the data programming system and the at least one additional first-stage router.
17. The computer system of claim 16 wherein the second base plate is stacked on top of the first base plate.
18. The computer system of claim 16 , further including a third-stage router that interrupts the communication paths between the data programming system and the first and the second second-stage routers.
19. The computer system of claim 18 wherein the third-stage router is a superconducting packet router and the communication paths between the third-stage router and each of the first and the second second-stage routers are superconducting.
20. The computer system of claim 18 wherein the third-stage router is an optical router and at least one communication path between the data programming system and the third-stage router and at least one of the communication paths between the third-stage router and each of the first and the second second-stage routers are optical signal paths.
21. The computer system of claim 10 , further including at least one optical-to-electrical signal converter.
22. The computer system of claim 16 , further comprising:
at least one additional base plate upon which is disposed at least one superconducting processor chip;
at least one additional communication path that establishes communication between the data programming system and at least one superconducting programmable device on the at least one additional base plate;
at least one additional first-stage router that interrupts a communication path between the data programming system and at least one superconducting programmable device on the at least one additional base plate;
at least one additional second-stage router that interrupts a communication path between the data programming system and the at least one additional first-stage router; and
at least one additional second-stage router that interrupts the communication paths between the data programming system and the at least one additional first-stage router.
23. The computer system of claim 22 wherein at least two base plates are stacked one on top of the other.