IP Library Granted Patent US 7,932,515
Granted Patent B2
US 7,932,515 · App. 12/194,282 · Granted Apr 26, 2011

Quantum processor

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Quick Facts
Patent No.
US 7,932,515
App. No.
12/194,282
Granted
Apr 26, 2011
Kind
B2
Abstract

Multiple substrates that carry quantum devices are coupled to provide quantum mechanical communicators therebetween, for example, using superconducting interconnects, vias, solder and/or magnetic flux. Such may advantageously reduce a footprint of a device such as a quantum processor.

Claims (29)

1. A multi-chip processor comprising:

a first plurality of quantum devices carried by a first substrate, wherein the first plurality of quantum devices includes a first set of qubits and a first set of couplers;

a second plurality of quantum devices carried by a second substrate, wherein the second plurality of quantum devices includes a second set of qubits and a second set of couplers; and

at least one multi-substrate coupler communicatively coupleable to a first quantum device of the first plurality of quantum devices and a second quantum device of the second plurality of quantum devices to couple quantum information therebetween.

2. The multi-chip processor of claim 1 wherein at least one of a quantum device from the first plurality of quantum devices, a quantum device from the second plurality of quantum devices and the multi-substrate coupler includes a loop of superconducting material interrupted by at least one Josephson junction.

3. The multi-chip processor of claim 1 wherein the multi-substrate coupler is configured to entangle the first quantum device of the first plurality of quantum devices and the second quantum device of the second plurality of quantum devices.

4. The multi-chip processor of claim 1 wherein the multi-substrate coupler comprises a first portion, a second portion and a third portion, the first portion of the multi-substrate coupler carried by the first substrate; the second portion of the multi-substrate coupler carried by the second substrate; and the third portion of the multi-substrate coupler superconductingly connects the first portion and the second portion.

5. The multi-chip processor of claim 4 wherein the third portion includes at least two superconducting solder bumps situated between the first substrate and the second substrate.

6. The multi-chip processor of claim 5 wherein the third portion further comprises at least two superconducting vias carried within the second substrate.

7. The multi-chip processor of claim 4 wherein the third portion includes superconducting wires within a multi-chip module.

8. The multi-chip processor of claim 4 wherein the first portion is communicatively coupleable to the first quantum device of the first plurality of quantum devices and the second portion is communicatively coupleable to the second quantum device of the second plurality of squantum devices.

9. The multi-chip processor of claim 1 wherein the multi-substrate coupler is carried by the first substrate and wherein a first magnetic flux inductor is configured to couple flux from the multi-substrate coupler to a second magnetic flux inductor from the second quantum device of the second plurality of quantum devices.

10. The multi-chip processor of claim 1 wherein at least one qubit from at least one of the first plurality of quantum devices and the second plurality of quantum devices is a superconducting flux qubit comprising a loop of superconducting material interrupted by at least one Josephson junction.

11. The multi-chip processor of claim 1 wherein the multi-substrate coupler is a superconducting coupler comprising a loop of superconducting material interrupted by at least one Josephson junction.

12. The multi-chip processor of claim 1 wherein the first substrate and the second substrate are packaged within a multi-chip module.

13. The multi-chip processor of claim 1 wherein the first substrate is packaged within a first multi-chip module and the second substrate is packaged within a second multi-chip module.

14. The multi-chip processor of claim 13 wherein the first multi-chip module is stacked on the second multi-chip module.

15. The multi-chip processor of claim 1 , further comprising:

at least a second multi-substrate coupler communicatively coupleable to at least a third quantum device of the first plurality of quantum devices and at least a fourth quantum device of the second plurality of quantum devices to couple quantum information therebetween.

16. A method of coupling quantum information between at least a first qubit carried by a first substrate and at least a second qubit carried by a second substrate, the method comprising:

coupling quantum information from the first qubit carried by the first substrate to the second qubit carried by the second substrate via a first multi-substrate coupler; and

coupling quantum information from the second qubit carried by the second substrate to the first qubit carried by the first substrate via the first multi-substrate coupler.

17. The method of claim 16 wherein coupling quantum information from the first qubit carried by the first substrate to the second qubit carried by the second substrate via a first multi-substrate coupler includes threading the first multi-substrate coupler with magnetic flux produced by current flowing within the first qubit carried by the first substrate and threading the second qubit carried by the second substrate with magnetic flux produced by current flowing within the first multi-substrate coupler.

18. The method of claim 16 wherein coupling quantum information from the second qubit carried by the second substrate to the first qubit carried by the first substrate via the first multi-substrate coupler includes threading the first multi-substrate coupler with magnetic flux produced by current flowing within the second qubit carried by the second substrate and threading the first qubit carried by the first substrate with magnetic flux produced by current flowing within the first multi-substrate coupler.

19. The method of claim 16 , further comprising:

entangling the first qubit carried by the first substrate and the second qubit carried by the second substrate via the first multi-substrate coupler.

20. The method of claim 16 , further comprising:

coupling quantum information from a third qubit carried by the first substrate to a fourth qubit carried by the second substrate via a second multi-substrate coupler; and

coupling quantum information from the fourth qubit carried by the second substrate to the third qubit carried by the first substrate via the second multi-substrate coupler.

Assignments (10)
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2025
From: PSPIB UNITAS INVESTMENTS II INC.
To: D-WAVE SYSTEMS INC.; 1372934 B.C. LTD.
Reel/Frame 070470/0098 →
INTELLECTUAL PROPERTY SECURITY AGREEMENT Recorded Apr 14, 2023
From: D-WAVE SYSTEMS INC.; 1372934 B.C. LTD.
To: PSPIB UNITAS INVESTMENTS II INC., AS COLLATERAL AGENT
Reel/Frame 063340/0888 →
RELEASE OF SECURITY INTEREST Recorded Sep 20, 2022
From: PSPIB UNITAS INVESTMENTS II INC., IN ITS CAPACITY AS COLLATERAL AGENT
To: D-WAVE SYSTEMS INC.
Reel/Frame 061493/0694 →
SECURITY INTEREST Recorded Mar 3, 2022
From: D-WAVE SYSTEMS INC.
To: PSPIB UNITAS INVESTMENTS II INC.
Reel/Frame 059317/0871 →
SECURITY INTEREST Recorded Nov 29, 2019
From: D-WAVE SYSTEMS INC.
To: BDC CAPITAL INC.
Reel/Frame 051144/0499 →
SECURITY INTEREST Recorded Mar 22, 2019
From: D-WAVE SYSTEMS INC.
To: BDC CAPITAL INC.
Reel/Frame 048674/0188 →
RELEASE OF SECURITY INTEREST Recorded Apr 13, 2017
From: VENTURE LENDING & LEASING VI, INC.; VENTURE LENDING & LEASING VII, INC.
To: D-WAVE SYSTEMS INC.
Reel/Frame 042252/0256 →
CORRECTIVE ASSIGNMENT TO REMOVE APPL. NO. 8733763 PREVIOUSLY RECORDED AT REEL: 034841 FRAME: 0497. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT. Recorded Jan 30, 2015
From: D-WAVE SYSTEMS INC.
To: VENTURE LENDING & LEASING VI, INC.; VENTURE LENDING & LEASING VII, INC.
Reel/Frame 034862/0237 →
SECURITY INTEREST Recorded Jan 29, 2015
From: D-WAVE SYSTEMS INC.
To: VENTURE LENDING & LEASING VI, INC.; VENTURE LENDING & LEASING VII, INC.
Reel/Frame 034841/0497 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 12, 2008
From: BUNYK, PAUL I.
To: D-WAVE SYSTEMS INC.
Reel/Frame 021822/0944 →