Voltage regulator for write/read assist circuit

1. A push-pull voltage regulator comprising:

(a) a voltage-up regulator, the voltage-up regulator having a plurality of inputs, an amplifier stage, and a biasing transistor, wherein the voltage-up regulator provides a reference voltage to an SRAM array;

(b) a voltage-down regulator, wherein the voltage-down regulator controls removal of excess charge from the SRAM array;

(c) a reference voltage source having an output;

(d) an offset voltage source having an output coupled between the output of the reference voltage source and an input of the voltage-down regulator;

(e) an output node of the push-pull voltage regulator coupled to the SRAM array through a voltage level switch; and

(e) a NMOS drainage transistor, a gate terminal of the NMOS drainage transistor coupled to an output of the voltage-down regulator, a first output terminal of the NMOS drainage transistor coupled to an output node of the push-pull voltage regulator, a second output terminal of the NMOS drainage transistor coupled to ground, wherein the NMOS drainage transistor transfers excess charge from the SRAM array to ground.

2. The push-pull voltage regulator of claim 1 , further comprising:

(f) a PMOS passgate transistor, a gate terminal of the PMOS passgate coupled to an output of the voltage-up regulator, and an output terminal of the PMOS passgate coupled to an output node of the push-pull voltage regulator, wherein biasing the PMOS pass-gate regulates the voltage at the output node of the push-pull voltage regulator.

3. The push-pull voltage regulator of claim 1 , further having:

(i) a voltage regulation state defined to provide the output of the reference voltage source to the SRAM array by the voltage-up regulator; and

(ii) a discharge operation state defined to selectively remove excess charge from the SRAM array controlled by the voltage-down regulator when the voltage of the output node of the push-pull voltage regulator is above a threshold voltage and the voltage-down regulator receives an input from an enable input, and threshold voltage is determined by the reference voltage source and the offset voltage source.

4. The push-pull voltage regulator of claim 1 , wherein the reference voltage source is coupled to a first input of the voltage-up regulator.

5. The push-pull voltage regulator of claim 1 , wherein the output node of the push-pull voltage regulator is coupled to a second input of the voltage-up regulator.

6. The push-pull voltage regulator of claim 1 , wherein the biasing transistor of the voltage-up regulator biases the voltage-up regulator for low power operation.

7. A voltage-down regulator controlling the removal of excess charge from a SRAM array comprising:

a plurality of a inputs;

a plurality of amplifier stages having an output, a first amplifier stage coupled to the plurality of inputs of a second amplifier stage;

a plurality of PMOS transistors, a first PMOS transistor coupling the plurality of inputs of the second amplifier stage to each other when turned on;

a plurality of inverters, the propagation delay of the plurality of inverters filters noise on the input of the second amplifier stage;

a gain amplifier coupled to the plurality of inverters, and the gain amplifier buffering the output of the plurality of amplifier stages;

an offset voltage source coupled to the plurality of inputs; and

a biasing transistor, the biasing transistor biases the voltage-down regulator for high current operation.

8. The voltage-down regulator of claim 7 , further comprising:

an enable input coupled to the voltage-down regulator, wherein the enable input activates the voltage-down regulator.

9. The voltage-down regulator of claim 7 , wherein a first input is coupled to the offset voltage source.

10. The voltage-down regulator of claim 7 , wherein a second input of the voltage-down regulator is coupled to an output node of a push-pull voltage regulator.

11. The gain amplifier of the voltage-down regulator of claim 7 , further comprising:

a two input NOR gate, coupled to the plurality of inverters of the voltage-down regulator; and

a plurality of inverters, buffering the output of the voltage-down regulator, and providing the output of the voltage-down regulator to a gate of a NMOS drainage transistor.

12. A method of voltage regulation and removing excess charge from an SRAM array comprising:

receiving an output of a reference voltage source at a first input of a voltage-up regulator;

providing the output of the reference voltage source to an SRAM array using the voltage-up regulator;

receiving feedback voltage at a second input of the voltage-up regulator from an output node of a push-pull voltage regulator;

maintaining a voltage regulation state for the SRAM array using feedback voltage from the output node of the push-pull voltage regulator;

receiving an output from an offset voltage source at a first input of a voltage-down regulator;

receiving feedback voltage at a second input of the voltage-down regulator from the output node of the push-pull voltage regulator; and

controlling a discharge operation state of the push-pull voltage regulator through the voltage-down regulator.

13. The method of voltage regulation of claim 12 , further comprising:

triggering the discharge operation state of the push-pull voltage regulator when the voltage-down regulator receives an enable input signal and the voltage of the output node of the push-pull voltage regulator is above a threshold voltage.

14. The method of voltage regulation of claim 13 , further comprising:

determining the threshold voltage using the output of the reference voltage source and an output of the offset voltage source.

15. The method of voltage regulation of claim 12 , wherein an output of a high power supply is higher than the output of the reference voltage source.

16. The method of voltage regulation of claim 12 , further comprising:

transmitting an output of the voltage-down regulator to a gate of a NMOS drainage transistor;

turning on the NMOS drainage transistor, a first output terminal of the NMOS drainage transistor coupled to the output node of the push-pull voltage regulator, a second output terminal of the NMOS drainage transistor coupled to ground; and

removing excess charge from the SRAM array through the NMOS drainage transistor.

17. The method of voltage regulation of claim 12 , further comprising:

biasing the gate terminal of the biasing transistor of the voltage-up regulator for low current operation.

18. The method of voltage regulation of claim 12 , further comprising:

biasing the gate terminal of the biasing transistor of the voltage-down regulator for high current operation.

19. The method of voltage regulation of claim 12 , further comprising:

continually providing the output of the reference voltage source to a voltage level switch.

20. The method of voltage regulation of claim 12 , further comprising:

equalizing a voltage a first input and a second input of a second amplifier stage of the voltage-down regulator before activation of the voltage-down regulator, wherein equalization of the first input and the second input of the second amplifier stage of the voltage-down regulator prevents noise transfer from a first amplifier stage of the voltage-down regulator.