IP Library Granted Patent US 8,285,789
Granted Patent B2
US 8,285,789 · App. 12/195,190 · Granted Oct 9, 2012

Flattened butterfly processor interconnect network

Assignee: Intel Corporation
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Quick Facts
Patent No.
US 8,285,789
App. No.
12/195,190
Granted
Oct 9, 2012
Kind
B2
Abstract

A multiprocessor computer system comprises a folded butterfly processor interconnect network, the folded butterfly interconnect network comprising a traditional butterfly interconnect network derived from a butterfly network by flattening routers in each row into a single router for each row, and eliminating channels entirely local to the single row.

Claims (19)

1. A multiprocessor computer system, comprising a flattened butterfly processor interconnect network, the flattened butterfly interconnect network comprising a network derived from a traditional butterfly processor interconnect network by flattening routers in each row into a single router for each row, and eliminating channels entirely local to the single row.

2. The multiprocessor computer system of claim 1 , wherein the flattened butterfly interconnect network further comprises forming two-way channels from the symmetrical links resulting from flattening a traditional butterfly interconnect network.

3. The multiprocessor computer system of claim 1 , further comprising network nodes that are operable to route data using at least one of minimal adaptive (MIN AD), Valiant's non-minimal oblivious algorithm (VAL), the UGAL non-minimal adaptive algorithm (UGAL), a variant of UGAL using sequential allocation (UGAL-S), and non-minimal adaptive routing in a flattened Clos (CLOS AD) routing algorithms.

4. The multiprocessor computer system of claim 1 , further comprising network nodes that are operable to route data using non-minimal globally-adaptive routing.

5. A data communication network, comprising a flattened butterfly processor network topology, the flattened butterfly network topology comprising a network derived from a traditional butterfly topology network by flattening routers in each row into a single router for each row, and eliminating channels entirely local to the single row.

6. The data communication network of claim 5 , wherein the flattened butterfly topology network further comprises forming two-way channels from the symmetrical links resulting from flattening a traditional butterfly topology network.

7. The data communication network of claim 5 , further comprising network nodes that are operable to route data using at least one of minimal adaptive (MIN AD), Valiant's non-minimal oblivious algorithm (VAL), the UGAL non-minimal adaptive algorithm (UGAL), a variant of UGAL using sequential allocation (UGAL-S), and non-minimal adaptive routing in a flattened Clos (CLOS AD) routing algorithms.

8. The data communication network of claim 5 , further comprising network nodes that are operable to route data using non-minimal globally-adaptive routing.

9. A method of operating a multiprocessor computer system, comprising communicating data between processing nodes via a flattened butterfly processor interconnect network, the flattened butterfly interconnect network comprising a network derived from a traditional butterfly processor interconnect network by flattening routers in each row into a single router for each row and eliminating channels entirely local to the single row.

10. The method of operating a multiprocessor computer system of claim 9 , wherein deriving the flattened butterfly interconnect network further comprises forming two-way channels from the symmetrical links resulting from flattening a traditional butterfly interconnect network.

11. The method of operating a multiprocessor computer system of claim 9 , wherein communicating data between processing nodes via a flattened butterfly processor interconnect network comprises routing data using at least one of minimal adaptive (MIN AD), Valiant's non-minimal oblivious algorithm (VAL), the UGAL non-minimal adaptive algorithm (UGAL), a variant of UGAL using sequential allocation (UGAL-S), and non-minimal adaptive routing in a flattened Clos (CLOS AD) routing algorithms.

12. The method of operating a multiprocessor computer system of claim 9 , wherein communicating data between processing nodes via a flattened butterfly processor interconnect network comprises routing data using non-minimal globally-adaptive routing.

13. A method of operating a communications network comprising communicating data in a flattened butterfly processor network topology, the flattened butterfly network topology comprising a network derived from a traditional butterfly topology network by flattening routers in each row into a single router for each row and eliminating channels entirely local to the single row.

14. The method of operating a communications network of claim 13 , wherein the flattened butterfly topology network further comprises forming two-way channels from the symmetrical links resulting from flattening a traditional butterfly topology network.

15. The method of operating a communications network of claim 13 , wherein communicating data between processing nodes via a flattened butterfly processor interconnect network comprises routing data using at least one of minimal adaptive (MIN AD), Valiant's non-minimal oblivious algorithm (VAL), the UGAL non-minimal adaptive algorithm (UGAL), a variant of UGAL using sequential allocation (UGAL-S), and non-minimal adaptive routing in a flattened Clos (CLOS AD) routing algorithms.

16. The method of operating a communications network of claim 13 , wherein communicating data between processing nodes via a flattened butterfly processor interconnect network comprises routing data using non-minimal globally-adaptive routing.

17. A multiprocessor computer system, comprising:

a flattened butterfly processor interconnect network.

18. A method of communicating data between processing nodes in a multiprocessor computer system, comprising routing data between nodes in a flattened butterfly topology.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 13, 2012
From: CRAY INC.
To: INTEL CORPORATION
Reel/Frame 028545/0797 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 30, 2009
From: KIM, JOHN; DALLY, WILLIAM J.
To: BOARD OF TRUSTEES OF THE LELAND STANFORD JUNIOR UNIVERSITY, THE
Reel/Frame 022190/0040 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 5, 2009
From: ABTS, DENNIS C.
To: CRAY INC.
Reel/Frame 022055/0095 →
Continuity (2)
Provisional Application 60977816 · Oct 5, 2007
Related Publication 20090106529A1 · Apr 23, 2009