Semiconductor apparatus and complimentary MIS logic circuit
View Patent ↗A configuration is adopted comprising an NchMOS transistor 1 equipped with an insulating isolation layer 4 providing insulation and isolation using an SOI structure, and a capacitor formed using an insulating film, with a silicon substrate B being made thin and substrate capacitance being reduced. The NchMOS transistor 1 is equipped with insulating isolation regions 5 a , 5 b that are perfectly depleted or partially depleted in a manner close to being perfectly depleted. An electrode 6 connected to a gate electrode G of the NchMOS transistor 1 and an impurity diffusion layer 7 are connected via a capacitor 2 . A source electrode S is connected to a power supply terminal 3 a , a gate electrode G is connected to an internal signal line S 1 , and a drain electrode D is connected to an internal signal line S 2 . Substrate bias voltage is then controlled using capacitor coupling when the NchMOS transistor 1 is turned on/off.
1. A semiconductor apparatus on a floating silicon substrate of an SOI (Silicon On Insulator) structure, wherein:
the semiconductor apparatus comprises:
a perfectly depleted or close to being perfectly depleted partially depleted-type MIS (Metal Insulator Semiconductor) transistor on the floating silicon substrate surrounded by an insulating isolation region and electrically insulated; and
a capacitor comprising two electrodes and an insulating film;
one electrode of the capacitor is connected to a gate electrode of the MIS transistor and the other electrode of the capacitor is connected to an impurity diffusion layer within the floating silicon substrate, the other electrode of the capacitor being diffused with same impurities as the floating silicon substrate, and different from a source and a drain of the MIS transistor; and
a BJT (Bipolar Junction Transistor) where the drain of the MIS transistor corresponds to a collector, the floating silicon substrate corresponds to a base, and the source of the MIS transistor corresponds to an emitter, and where, when gate voltage with respect to the source is V GS , gate capacitance of the MIS transistor is C G , capacitance of the capacitor is C C , parasitic capacitance is C P , clamp voltage of the BJT is V C , and a floating silicon substrate potential immediately prior to change in gate potential is V B(I) , then V B(I) +(C G +C C )*V GS /(C G +C C +C P )>V C .
2. The semiconductor apparatus of claim 1 , wherein the impurity concentration of the impurity diffusion layer diffused with the same impurities as the floating silicon substrate is at least ten times greater than the impurity concentration of the floating silicon substrate.
3. The semiconductor apparatus of claim 1 , wherein the impurity diffusion layer is arranged so as to surround a periphery of the MIS transistor.