Semiconductor device and fabricating method thereof
View Patent ↗A semiconductor device and fabricating method thereof are disclosed, by which channel mobility is enhanced and by which effect of flicker noise can be minimized. Embodiments relate to a method of fabricating a semiconductor device which includes forming a first epi-layer over a substrate, forming a second epi-layer over the first epi-layer, forming a gate electrode over the second epi-layer, forming a spacer over both sides of the gate electrode, etching an area adjacent both sides of the spacer to a depth of the substrate, forming an LDD region in a region under the spacer, and forming a third epi-layer for a source/drain region over the etched area adjacent both of the sides of the spacer.
1. A method comprising:
forming a first epi-layer over a substrate;
forming a second epi-layer over the first epi-layer;
forming a gate electrode over the second epi-layer;
forming a spacer over both sides of the gate electrode;
etching an area adjacent both sides of the spacer to a depth of the substrate;
ion implanting an LDD region in a region under the spacer after said etching; and
forming a third epi-layer for a source/drain region over the etched area adjacent both of the sides of the spacer.
2. The method of claim 1 , wherein the first epi-layer is doped with channel impurity.
3. The method of claim 1 , wherein the second epi-layer is formed without additional channel dopants.
4. The method of claim 1 , wherein the first and second epi-layers are substantially the same thickness.
5. The method of claim 4 , wherein each of the first and second epi-layers is between 10 and 30 nm thick.
6. The method of claim 1 , wherein forming a spacer over both sides of the gate electrode comprises:
forming an oxide layer over the second epitaxial layer adjacent both sides of the gate electrode;
forming a first nitride layer over the gate electrode, the nitride layer having a width greater than that of the gate electrode, and extending over the top of the oxide layer; and
removing a portion of the oxide layer using the first nitride layer as a mask.
7. The method of claim 6 , wherein the first nitride layer is further used as a mask in etching the first and second epi-layers to the depth of the substrate after forming the spacer.
8. The method of claim 7 , wherein the first nitride layer is removed after etching the first and second epi-layers to the depth of the substrate.
9. The method of claim 6 , wherein the first nitride layer extends beyond the gate electrode by about 45 nm˜55 nm.
10. The method of claim 1 , wherein after etching the area adjacent both of the sides of the spacer to the depth of the substrate, the method comprises applying a vertical stress to the substrate exposed by the etching.
11. The method of claim 10 , the step of applying the stress to the substrate in the vertical direction, comprising the step of forming a second nitride layer over the substrate including the gate electrode and the spacer.
12. The method of claim 11 , wherein the second nitride layer is formed of SiN.
13. The method of claim 11 , comprising removing the second nitride layer.
14. The method of claim 10 , wherein the stress is memorized in a channel region of the gate electrode.
15. The method of claim 10 , wherein the gate electrode is formed about 130˜170 nm tall.
16. The method of claim 10 , wherein the stress is concentrated vertically with respect to a channel region under the gate electrode by high-temperature annealing.