Reconfigurable semiconductor device
View Patent ↗A reconfigurable semiconductor device is disclosed. The semiconductor device includes a substrate, a first insulating material formed on the substrate, two channels having different polarities, a plurality of terminal electrodes formed on the insulating material and coupled in common with the channels at their opposite ends, a second insulating material formed on the terminal electrodes, and a control gate formed on the second insulating material. The channels have different polarity and a charge storage layer is formed inside the second insulating material. The control gate is applied with a forward bias or a reverse bias and then the bias is cut off. The voltage-current characteristics of the semiconductor device are changed according to an electrical charge created in the charge storage layer.
1. A semiconductor device comprising:
an operating gate;
a substrate formed on the operating gate;
a first insulating layer formed on the substrate;
a first channel having a first polarity that is formed at a first planar position of the first insulating layer;
a second channel having a second polarity that is formed at a second planar position of the first insulating layer;
terminal electrodes coupled in common with the first channel and the second channel at their opposite ends;
a second insulating layer formed on the channels and the terminal electrodes;
a charge storage layer floated inside the second insulating layer and chargeable with an electrical charge; and
at least one control gate formed on the second insulating layer.
2. The semiconductor device of claim 1 , wherein the charge storage layer is formed at a location corresponding with the first planar position and the second planar position.
3. The semiconductor device of claim 1 , wherein the first channel is a p-type doped semiconductor layer and the second channel is an n-type doped semiconductor layer.
4. The semiconductor device of claim 1 , wherein the first channel is a p-type doped nanowire and the second channel is an n-type doped nanowire.
5. The semiconductor device of claim 1 , wherein a lower insulating sub-layer is formed between the charge storage layer and the channel, and is thin enough for tunneling to be possible.
6. The semiconductor device of claim 1 , wherein the charge storage layer comprises a plurality of conductive particles.
7. The semiconductor device of claim 6 , wherein the conductive particles are nanoparticles.
8. The semiconductor device of claim 1 , wherein a forward bias or a reverse bias is applied to the control gate to control the operating characteristics of the semiconductor device.
9. The semiconductor device of claim 1 , wherein a negative charge is charged in at least one part of the charge storage layer when a forward bias is applied to the control gate.
10. The semiconductor device of claim 1 , wherein a positive charge is charged in at least one part of the charge storage layer when reverse bias is applied to the control gate.
11. The semiconductor device of claim 1 , wherein at least one of the control gates includes a first control gate corresponding with the first channel and a second control gate corresponding with the second channel.
12. A semiconductor device comprising:
an operating gate;
at least a first and second channels formed above the operating gate and insulated from the operating gate, and wherein both the first and second channels have a first end and a second end;
a first terminal electrode adapted to couple together the first end of the first channel and the first end of the second channel,
a second terminal electrode adapted to couple together the second end of the first channel and the second end of the second channel;
a charge storage layer arranged adjacent to the first and second channels but insulated from the first and second channels; and
at least one control gate formed above the charge storage layer and insulated from the charge storage layer,
wherein the first channel comprises a p-type channel and the second channel comprises an n-type channel.
13. The semiconductor device of claim 12 , wherein an absolute electrical potential of the operating gate required for a current to flow above a critical value through the p-type channel is reduced when, after the application of a forward bias to the operating gate, the bias is cut off.
14. The semiconductor device of claim 12 , wherein an absolute electrical potential of the operating gate required for a current to flow above a critical value through the second channel is reduced when, after the application of a reverse bias to the operating gate, the bias is cut off.
15. The semiconductor device of claim 12 , wherein the control gate includes a first control gate corresponding with the first channel and a second control gate corresponding with the second channel.
16. The semiconductor device of claim 15 , wherein a forward bias is applied to the first control gate and a reverse bias is applied to the second control gate.
17. The semiconductor device of claim 12 , wherein the first channel and the second channel are nanowires.
18. The semiconductor device of claim 12 , wherein the charge storage layer comprises a plurality of nanoparticles.
19. A method of manufacturing a semiconductor device, comprising:
forming a first insulating layer on a substrate;
forming a first channel having a first polarity at a first planar position of the first insulating layer and a second channel having a second polarity at a second planar position of the first insulating layer;
forming a plurality of terminal electrodes coupled in common with the first channel and the second channel at their opposite ends;
forming a second insulating layer on the channel and the terminal electrodes;
forming a charge storage layer on the second insulating layer that is chargeable with an electrical charge and that corresponds with the first planar position and the second planar position;
forming a third insulating layer on the charge storage layer; and
forming an operating gate below the first insulating layer and a control gate on the third insulating layer.
20. The method of claim 19 , wherein the first channel and the second channel are nanowires formed in a nanowire solution.
21. The method of claim 20 further comprising forming a film that prevents nanowire adsorption on a remaining region except for the first planar position and the second planar position.
22. The method of claim 21 , wherein the film that prevents nanowire adsorption is an octadecyltrichlorosilane molecular film.
23. The method of claim 19 , wherein the charge storage layer is formed with a plurality of nanoparticles.
24. The method of claim 23 further comprising forming a linker film for the adsorption of nanoparticles on at least one part of the second insulating layer.
25. The method of claim 24 , wherein the linker film is an aminopropylethoxysilane (APTES) film.
26. The method of claim 19 , wherein the terminal electrodes comprise gold or titanium.