IP Library Patent Application 12198746
Patent Application
App. No. 12/198,746

METHOD OF MANUFACTURING DISPLAY DEVICE AND DISPLAY DEVICE THEREFROM

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Quick Facts
Patent No.
US None
App. No.
12/198,746
Abstract

A method of manufacturing a display device includes: forming an auxiliary layer including at least one of metal and a metal oxide on an insulating substrate; forming a photoresist layer pattern partially exposing the auxiliary layer on the auxiliary layer; forming a trench on the insulating substrate by etching the exposed auxiliary layer and the insulating substrate under the exposed auxiliary layer; forming a seed layer including a first seed layer disposed on the photoresist layer pattern and a second seed layer disposed in the trench; removing the photoresist layer pattern and the first seed layer by lifting off the photoresist layer pattern; removing the auxiliary layer remaining on the insulating substrate after lifting off the photoresist layer pattern; and forming a main wiring layer on the second seed layer by electroless plating.

Claims (26)

1 . A method of manufacturing a metal wiring comprising:

forming an auxiliary layer on an insulating substrate;

forming a photoresist layer pattern on the auxiliary layer, the photoresist layer partially exposing the auxiliary layer on the insulating substrate;

forming a trench in the insulating substrate by etching the exposed auxiliary layer and the insulating substrate under the exposed auxiliary layer;

forming a seed layer including a first seed layer disposed on the photoresist layer pattern and a second seed layer disposed in the trench;

removing the photoresist layer pattern and the first seed layer by lifting off the photoresist layer pattern;

removing the auxiliary layer remaining on the insulating substrate after lifting off the photoresist layer pattern; and

forming a main wiring layer on the second seed layer by electroless plating.

2 . The method according to claim 1 , wherein the auxiliary layer comprises at least one of molybdenum (Mo), a molybdenum alloy, chrome (Cr), copper (Cu), a copper alloy, aluminum (Al), an aluminum alloy, silver (Ag), a silver alloy an indium-tin-oxide and indium-zinc-oxide.

3 . The method according to claim 2 , wherein the auxiliary layer has a thickness of 50 Å to 3000 Å.

4 . The method according to claim 2 , wherein the seed layer comprises at least one of molybdenum (Mo), a molybdenum alloy, chrome (Cr), copper (Cu), a copper alloy, a copper oxide, aluminum (Al), an aluminum alloy, silver (Ag), a silver alloy, titanium (Ti), and a titanium alloy, wherein the seed layer has a etch selectivity with the auxiliary layer.

5 . The method according to claim 4 , wherein the main wiring layer comprises at least one of copper and silver.

6 . The method according to claim 5 , wherein the main wiring layer has a thickness of 0.3 μm to 2 μm.

7 . The method according to claim 1 , wherein the main wiring layer comprises at least one of copper and silver.

8 . The method according to claim 7 , wherein the main wiring layer has a thickness of 0.3 μm to 2 μm.

9 . The method according to claim 1 , forming a trech in the insulating substrate further comprises forming an undercut under the photoresist layer pattern.

10 . The method according to claim 9 , wherein the auxiliary layer comprises at least one of molybdenum (Mo), a molybdenum alloy, chrome (Cr), copper (Cu), a copper alloy, aluminum (Al), an aluminum alloy, silver (Ag), a silver alloy an indium-tin-oxide and indium-zinc-oxide.

11 . The method according to claim 10 , wherein the auxiliary layer has a thickness of 50 Å to 3000 Å.

12 . The method according to claim 10 , wherein the seed layer comprises at least one of molybdenum (Mo), a molybdenum alloy, chrome (Cr), copper (Cu), a copper alloy, a copper oxide, aluminum (Al), an aluminum alloy, silver (Ag), a silver alloy, titanium (Ti), and a titanium alloy, wherein the seed layer has a etch selectivity with the auxiliary layer.

13 . The method according to claim 12 , wherein the main wiring layer comprises at least one of copper and silver.

14 . The method according to claim 13 , wherein the main wiring layer has a thickness of 0.3 μm to 2 μm.

15 . A wiring structure comprising:

an insulating substrate where a trench is formed; and

a wiring layer disposed in the trench including a copper oxide layer directly contacting with the insulating substrate and a copper layer disposed on the copper oxide layer.

16 . The wiring structure according to claim 15 , wherein the copper layer has a thickness of 0.3 μm to 2 μm.

17 . The wiring structure according to claim 16 , wherein the copper layer is disposed substantially in the trench.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 20, 2012
From: SAMSUNG ELECTRONICS CO., LTD.
To: SAMSUNG DISPLAY CO., LTD.
Reel/Frame 028992/0053 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 28, 2008
From: LEE, BYEONG-JIN; PARK, HONG-SICK; NING, HONG-LONG; JEONG, CHANG-OH; BAE, YANG-HO; YUN, PIL-SANG; CHO, SUNG-HEN; SONG, KI-YONG; JUNG, SEUNG-JAE; KIM, BYEONG-BEOM
To: SAMSUNG ELECTRONICS CO., LTD
Reel/Frame 021458/0152 →