Variation tolerant network on chip (NoC) with self-calibrating links

1. A self correcting device, comprising:

a. a first flip-flop to receive data and coupled to a clock input;

b. one or more delayed flip-flops used to detect delay variations;

c. a multiplexer coupled to the output of the first flip-flop and the delayed flip-flops,

d. a metastability detector and error check controller to control the multiplexer to select one flip-flop output; and

e. an adaptive voltage swing link coupled to the multiplexer output to generate a voltage swing on the link based on a selected clock skew.

2. The device of claim 1 , wherein each delayed flip-flop receives the data input and a delayed version of the clock input.

3. The device of claim 1 , wherein the controller selects data from the first flip-flop if there is no process variation.

4. The device of claim 1 , wherein the flip-flops form a timing chain and wherein the controller compares all flip-flop outputs with the output of the most delayed flip-flop and when the output of a flip-flop differs or is metastable, the next flip-flop output in the timing chain is selected for reliable operation.

5. The device of claim 1 , comprising a swing voltage driver coupled to a multiplexer output.

6. The device of claim 5 , wherein the swing voltage driver is adaptive.

7. The device of claim 5 , wherein the swing voltage driver comprises a sense-amplifier-based flip-flop (SAFF).

8. The device of claim 5 , comprising a receiver coupled to the swing voltage driver.

9. The device of claim 8 , wherein the receiver comprises a pseudo-differential circuit (PDIFF).

10. A method for operating a self-correcting device including a flip-flop to receive data input and a clock input; a detection and correction unit; a multiplexer coupled to the output of the flip-flop and the detection and correction unit, and a metastability detector and error check controller to control the multiplexer, the method comprising:

a. performing post-fabrication testing of the self-correcting device;

b. calibrating the self-correcting device;

c. selecting a path through the flip-flop and the detection and correction unit that compensates for delay variations; and

d. operating the self-correcting device after calibration.

11. The method of claim 10 , comprising periodically re-calibrating the device.

12. The method of claim 11 , comprising providing input patterns to a statistical static timing analysis (SSTA).

13. The method of claim 11 , comprising powering down components that do not belong to the selected path to save power.

14. The method of claim 11 , comprising powering down unused flip-flops in the device.

15. A system, comprising:

a. a network-on-chip (NoC) device having a plurality of sub-units; and

b. a variation tolerant switch-to-switch link coupling the sub-units, wherein the link automatically detects delay variations and compensates for the delay variations;

wherein the link comprises a self-correcting device, said self-correcting device comprising:

i. a first flip-flop to receive data and coupled to a clock input;

ii. one or more delayed flip-flops used to detect delay variations;

iii. a multiplexer coupled to the output of the first flip-flop and the delayed flip-flops,

iv. a metastability detector and error check controller to control the multiplexer to select one flip-flop output; and

v. an adaptive voltage swing link coupled to the multiplexer output to generate a voltage swing on the link based on a selected clock skew.

16. The system of claim 15 , comprising a tester to perform

post-fabrication testing of the self-correcting device;

calibrate the self-correcting device; and

select a path through a pool of flip-flops to compensate for delay variations.

17. The system of claim 16 , wherein the tester does one of: periodically recalibrates the self-correcting device, powers down unused flip-flops in the self-correcting device and performs statistical static timing analysis (SSTA).