Memory power management
A memory system is described, where a plurality of memory modules is connected to a memory controller. The power status of each of the memory modules is controlled, depending on the functions being performed by the memory module. When no read or write operation is being performed on a particular memory module, at least a portion of the circuitry may be operated in a lower power mode. A memory circuit associated with the memory module may be placed in a low power mode by disabling a clock. The memory circuit data integrity may be secured by issuing refresh commands while when the memory circuit is in the lower power mode, by enabling the clock, issuing the refresh command, and disabling the clock after completion of the refresh operation.
1. A memory module, comprising:
a controller configured to initiate an autorefresh operation and to provide a clock signal and a clock control; and
a plurality of volatile dynamic random access memory (DRAM) circuits, each DRAM circuit having:
a clock signal input; and
a clock control comprising a state of enabled or disabled and the clock control is set to enabled during performance of a write operation, or a read operation,
wherein when the controller determines that the state of the clock control of the DRAM circuit is disabled and an autorefresh operation is to be performed, the state of the clock control is set to enabled and an autorefresh operation command is issued by the controller to the DRAM circuit to initiate an autorefresh operation of the DRAM circuit, and the state of the clock control is set to disabled after completion of the autorefresh operation; and, a transition between any one of the write operation, the read operation, or the autorefresh operation is made without performing a selfrefresh operation; and
wherein the clock control state is disabled without performing a concurrent selfrefresh operation for the DRAM circuit.
2. The memory module of claim 1 , wherein the state of the clock control of a first DRAM circuit of the plurality of DRAM circuits is independent of the state of the clock control of a second DRAM circuit of the plurality of DRAM circuits.
3. The memory module of claim 1 , wherein the autorefresh operation of a first DRAM circuit of the plurality of DRAM circuits is independent of the autorefresh operation of a second DRAM circuit of the plurality of DRAM circuits.
4. The memory module of claim 1 , wherein the autorefresh operation is a plurality of autorefresh operations.
5. The memory module of claim 1 , wherein a time interval between autorefresh commands issued by the controller is determined based on a temperature of the DRAM circuit.
6. The memory module of claim 5 , wherein each DRAM circuit has a current temperature and the time interval depends on a highest current temperature of the plurality of DRAM circuits on the memory module.
7. The memory module of claim 1 , wherein the autorefresh operation is performed by issuing periodic autorefresh commands.
8. The memory module of claim 1 , wherein a plurality of memory modules are connectable to a bus, and autorefresh operations of a first memory module are independent of autorefresh operations of a second memory module.
9. A method of managing a memory system, the method comprising:
providing a plurality of memory modules, the modules having a bus interface, a memory circuit, and a controller;
providing a bus, the bus providing connectivity between a root memory module of the plurality of memory modules and a memory controller, such that a first memory module and a second memory module of the plurality of memory modules are connected to the root memory module by the bus; and
for each of the first memory module and the second memory module, determining using the controller at the respective memory module:
if a read or a write operation is being performed on the memory circuit of the memory module, setting a clock control state to enabled during performance of a write operation, or a read operation; or
if a read or a write operation is not being performed setting the dock control state to disabled;
determining whether an autorefresh operation is needed to maintain validity of data stored in the memory module; and
if an autorefresh operation is required, setting the clock control state to enabled and issuing an autorefresh command to the memory circuit;
and, a transition between any one of the write operation, the read operation, or the autorefresh operation is made without performing a selfrefresh operation; and
wherein the clock control state is disabled without performing a concurrent selfrefresh operation for the memory circuit.
10. The method of claim 9 , further comprising determining whether data is being transmitted to another memory module, or is expected to be received from another memory module, and placing one or more bus interfaces of the memory module in a low power state when no data is being transmitted, or expected to be transmitted.
11. A computer program product, stored in a non-transitory computer readable memory, comprising:
instructions executable by a controller of a memory module to:
determine if a read or a write operation is requested or in progress on a volatile dynamic random access memory (DRAM) memory circuit of the memory module; and,
when the read or the write operation is neither requested nor in progress:
set a clock state of the DRAM memory circuit to disabled; determine if the DRAM memory circuit should be refreshed
if the DRAM memory circuit should be refreshed, set, the clock state to enabled and issue an autorefresh command to the DRAM memory circuit;
set the clock state to disabled when an autorefresh
operation in response to the auto refresh command has been completed; or,
if the DRAM memory circuit should not be refreshed, continue to determine if the read or write operation is requested or in progress,
wherein the autorefresh operation is performed in response to the autorefresh command; and, a transition between any one of the write operation, the react operation, a the autorefresh operation is made without performing a selfrefresh operation; and
wherein the dock state is disabled without performing a concurrent selfrefresh operation for the DRAM memory circuit.
12. The computer program product of claim 11 , wherein the controller is configured to issue a sufficient number of autorefresh commands during a predetermined time interval to maintain validity of data stored in the DRAM memory circuit.
13. The computer program product of claim 11 , where a maximum number of consecutive autorefresh commands is equal to the plurality of rows of the memory circuit.
14. The computer program product of claim 13 , wherein the clock control state is set to enabled during consecutive autorefresh commands.
15. A method of managing a memory system, the method comprising:
providing a plurality of volatile dynamic random access memory (DRAM) memory circuits, each memory circuit capable of performing an autorefresh operation and capable of receiving a clock signal and a dock state, wherein the clock state is enabled during a time period where a read or a write operation is being performed and is disabled when the step of performing the read operation or the write operation has been completed;
providing a processor communicating with the DRAM memory circuits; determining using the processor, if a DRAM memory circuit of the plurality of DRAM memory circuits is performing the read operation or the write operation; and
if the DRAM memory circuit is not performing the read operation or the write operation:
setting the clock control state to enabled and issuing an autorefresh command;
setting the dock state to disabled in response to completion of performing an autorefresh operation in response to the autorefresh command; or,
if the memory circuit is performing the read or the write operation; waiting for the read operation or the write operation to
complete; and
repeating the step of determining,
wherein, a transition between any one of the write operation, the read operation, a standby operation, or the autorefresh operation is made without performing a self-refresh operation; and
wherein the clock state is disabled without performing a concurrent selfrefresh operation for the DRAM memo circuit.
16. The method of claim 15 , wherein the autorefresh command is a plurality of autorefresh commands to be performed prior to setting the clock control state to disabled.