Granted Patent B2

US 8,411,853 · App. 12/200,037 · Granted Apr 2, 2013

Inventors: Paul G. Filseth (Los Gatos, CA); Mikhail Grinchuk (San Jose, CA); Anatoli Bolotov (Cupertino, CA); Lav D. Ivanovic (Sunnyvale, CA)

Assignee: LSI Corporation

Abstract

Claims (63)

1. An apparatus comprising:

a first circuit configured to (i) generate a second plurality of Galois Field elements by performing a first Galois Field inversion on a first plurality of Galois Field elements, said first Galois Field inversion being different from a second Galois Field inversion defined by an Advanced Encryption Standard and (ii) generate a third plurality of Galois Field elements by multiplying said second Galois Field elements by an inverse of a first predetermined matrix; and

a second circuit configured to (i) generate a fourth plurality of Galois Field elements by processing said third Galois Field elements in a current encryption round while in a non-skip mode, (ii) generate a fifth plurality of Galois Field elements by multiplying said fourth Galois Field elements by said first predetermined matrix and (iii) present said fifth Galois Field elements as updated versions of said first Galois Field elements in advance of a next encryption round.

2. The apparatus according to claim 1 , wherein said second circuit is further configured to present said third Galois Field elements as said fourth Galois Field elements while in a skip mode.

3. The apparatus according to claim 1 , wherein said second circuit is further configured to (i) generate a sixth plurality of Galois Field elements by shifting said third Galois Field elements and (ii) generate a seventh plurality of Galois Field elements by multiplying said sixth Galois Field elements by a plurality of second predetermined matrices.

4. The apparatus according to claim 1 , further comprising a third circuit configured to (i) generate a sixth plurality of Galois Field elements by processing said third Galois Field elements in a current decryption round, (ii) generate a seventh plurality of Galois Field elements by multiplying said sixth Galois Field elements by both said first predetermined matrix and a second predetermined matrix and (iii) present said seventh Galois Field elements as updated versions of said first Galois Field elements in advance of a next decryption round.

5. The apparatus according to claim 3 , wherein said second circuit is further configured to (i) generate an eighth plurality of Galois Field elements by exclusive OR'ing said seventh Galois Field elements and (ii) generating said fourth Galois Field elements by exclusive OR'ing said eighth Galois Field elements with a round key.

6. A method of encryption, comprising the steps of:

(A) generating a second plurality of Galois Field elements by performing a first Galois Field inversion on a first plurality of Galois Field elements, said first Galois Field inversion being different from a second Galois Field inversion defined by an Advanced Encryption Standard;

(B) generating a third plurality of Galois Field elements by multiplying said second Galois Field elements by an inverse of a first predetermined matrix;

(C) generating a fourth plurality of Galois Field elements by processing said third Galois Field elements in a current encryption round while in a non-skip mode; and

(D) generating a fifth plurality of Galois Field elements by multiplying said fourth Galois Field elements by said first predetermined matrix.

7. The method according to claim 6 , further comprising the step of:

presenting said third Galois Field elements as said fourth Galois Field elements while in a skip mode.

8. The method according to claim 6 , further comprising the steps of:

generating a sixth plurality of Galois Field elements by shifting said third Galois Field elements; and

generating a seventh plurality of Galois Field elements by multiplying said sixth Galois Field elements by a plurality of second predetermined matrices.

9. The method according to claim 6 , wherein said first Galois Field inversion comprises a Galois Field (16) inversion having (i) a plurality of input bits x, y, z, and t, (ii) a plurality of output bits X, Y, Z and T and (iii) the functions of:

F01=x AND z;

F02=x AND (NOT t);

F03=y AND (NOT t);

F04=x OR z;

F05=(NOT y) AND t;

F06=x AND F05;

F07=F01 OR F03;

F08=(NOT F01) AND y;

F09=F04 AND (NOT F05);

F10=F03 OR F05;

F11=F02 AND (NOT F08);

F12=F07 AND (NOT F09);

F13=(NOT F02) AND F08;

F14=F06 OR y;

F15=(NOT x) AND F09;

F16=(NOT F07) AND F04;

F17=(NOT F16) AND F10;

Y=F14 AND (NOT F15);

X=F11 OR F13;

Z=F12 OR F16; and

T=F15 OR F17.

10. The method according to claim 8 , further comprising the steps of:

generating an eighth plurality of Galois Field elements by exclusive OR'ing said seventh Galois Field elements; and

generating said fourth Galois Field elements by exclusive OR'ing said eighth Galois Field elements with a round key.

11. An apparatus comprising:

a first circuit configured to (i) generate a second plurality of Galois Field elements by performing a first Galois Field inversion on a first plurality of Galois Field elements, said first Galois Field inversion being different from a second Galois Field inversion defined by an Advanced Encryption Standard and (ii) generate a third plurality of Galois Field elements by multiplying said second Galois Field elements by an inverse of a first predetermined matrix; and

a second circuit configured to (i) generate a fourth plurality of Galois Field elements by processing said third Galois Field elements in a current decryption round and (ii) generate a fifth plurality of Galois Field elements by multiplying said fourth Galois Field elements by both said first predetermined matrix and a second predetermined matrix while in a non-skip mode.

12. The apparatus according to claim 11 , further comprising a third circuit configured to generate said fifth Galois Field elements by multiplying said third Galois Field elements by said first predetermined matrix while in a skip mode.

13. The apparatus according to claim 11 , wherein said second circuit is further configured to (i) generate a sixth plurality of Galois Field elements by exclusive OR'ing said third Galois Field elements with a round key and (ii) generate a seventh plurality of Galois Field elements by multiplying said sixth Galois Field elements by a plurality of third predetermined matrices.

14. The apparatus according to claim 13 , wherein said second circuit is further configured to generate an eighth plurality of Galois Field elements by exclusive OR'ing said seventh Galois Field elements.

15. The apparatus according to claim 14 , wherein said second circuit is further configured to generate said fourth Galois Field elements by inverse shifting said eighth Galois Field elements.

16. A method of decryption, comprising the steps of:

(A) generating a second plurality of Galois Field elements by performing a first Galois Field inversion on a first plurality of Galois Field elements, said first Galois Field inversion being different from a second Galois Field inversion defined by an Advanced Encryption Standard;

(B) generating a third plurality of Galois Field elements by multiplying said second Galois Field elements by an inverse of a first predetermined matrix;

(C) generating a fourth plurality of Galois Field elements by processing said third Galois Field elements in a current decryption round; and

(D) generating a fifth plurality of Galois Field elements by multiplying said fourth Galois Field elements by both said first predetermined matrix and a second predetermined matrix while in a non-skip mode.

17. The method according to claim 16 , further comprising the step of:

presenting said fifth Galois Field elements by multiplying said third Galois Field elements by said first predetermined matrix while in a skip mode.

18. The method according to claim 17 , further comprising the steps of:

generating a sixth plurality of Galois Field elements by exclusive OR'ing said third Galois Field elements with a round key; and

generating a seventh plurality of Galois Field elements by multiplying said sixth Galois Field elements by a plurality of third predetermined matrices.

19. The method according to claim 18 , further comprising the step of:

generating an eighth plurality of Galois Field elements by exclusive OR'ing said seventh Galois Field elements.

20. The method according to claim 19 , further comprising the step of:

generating said fourth Galois Field elements by inverse shifting said eighth Galois Field elements.

Assignments (8)

Continuity (1)