Flash memory and manufacturing method of the same

1. A flash memory comprising:

a shallow trench isolation layer and an active region formed at a substrate;

a plurality of stacked gates formed on the active region;

a deep implant region formed at a lower side of the shallow trench isolation layer and the active region between the stacked gates; and

a shallow implant region formed at a surface of the active region between the stacked gates, wherein the deep implant region comprises:

a first ion implantation region formed at the active region between the stacked gates at a depth less than that of the shallow trench isolation layer;

a second ion implantation region formed at the active region between the stacked gates at a depth greater than that of the first ion implantation region; and

a third ion implantation region formed at the lower region of the shallow trench isolation layer and the active region between the stacked gates at a depth greater than that of the shallow trench isolation layer,

wherein the third ion implantation region is connected in a straight line to the lowermost portion of the shallow trench isolation layer and the active region between the stacked gates.

2. The flash memory of claim 1 , wherein each of the stacked gates has a height greater than the depth of the shallow trench isolation layer.

3. The flash memory of claim 1 , wherein the second ion implantation region is formed between the first ion implantation region and the third ion implantation region.

4. The flash memory of claim 1 , wherein the shallow implant region is electrically connected to an upper side of the deep implant region.

5. The flash memory of claim 1 , wherein the deep implant region and the shallow implant region form a common source.