IP Library Granted Patent US 8,053,792
Granted Patent B2
US 8,053,792 · App. 12/201,987 · Granted Nov 8, 2011

Semiconductor light emitting device and method for manufacturing the same

Assignee: LG Innotek Co., Ltd.
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Quick Facts
Patent No.
US 8,053,792
App. No.
12/201,987
Granted
Nov 8, 2011
Kind
B2
Abstract

Provided is a semiconductor light emitting device and a method for manufacturing the same. The semiconductor light emitting device comprises: a first semiconductor layer; a light emitting structure on one sided portion of the first semiconductor layer; a protection device structure on the other sided portion of the first semiconductor layer; and a first electrode layer on the protection device structure.

Claims (33)

1. A semiconductor light emitting device comprising:

a substrate;

an N-type first semiconductor layer on the substrate;

a light emitting structure on a first area of the N-type first semiconductor layer;

a protection device structure on a second area of the N-type first semiconductor layer; and

a first electrode layer on the protection device structure,

wherein the light emitting structure comprises: an N-type second semiconductor layer on the first area of the N-type first semiconductor layer; an active layer on the N-type second semiconductor layer; and a P-type first semiconductor layer on the active layer,

wherein the protection device structure comprises: a P-type second semiconductor layer on the second area of the N-type first semiconductor layer; and an N-type third semiconductor layer on the P-type second semiconductor layer, and

wherein the N-type first semiconductor layer, the P-type second semiconductor layer, and the N-type third semiconductor layer form an N-P-N junction, and when a reverse ESD is applied to the first electrode, the reverse ESD flows and dissipates through the N-P-N junction.

2. The semiconductor light emitting device of claim 1 , wherein the N-type first semiconductor layer and the N-type second semiconductor layer satisfy a composition formula of In x Al y Ga 1-x-y N (0≦x≦1, 0≦y≦1, 0≦x+y≦1) as N-type semiconductor layers.

3. The semiconductor light emitting device of claim 1 , wherein the P-type second semiconductor layer comprises a single layer or superlattice structure selected from the group consisting of GaN, InN, AlN, InGaN, AlGaN, InAlGaN and AlInN as a P-type semiconductor layer.

4. The semiconductor light emitting device of claim 1 , wherein the N-type third semiconductor layer comprises a single layer or superlattice structure selected from the group consisting of GaN, InN, AlN, InGaN, AlGaN, InAlGaN and AlInN as an N-type semiconductor layer.

5. The semiconductor light emitting device of claim 1 , wherein the P-type second semiconductor layer is formed in a thickness range of 5 Å to 500 Å to form a tunnel junction with the N-type first semiconductor layer, and the N-type third semiconductor layer is formed in a thickness range of 10 Å to 3 μm.

6. The semiconductor light emitting device of claim 1 , comprising at least one of a second electrode layer, a transparent electrode layer and an N-type fourth semiconductor layer on the P-type first semiconductor layer.

7. The semiconductor light emitting device of claim 1 , comprising at least one of an undoped semiconductor layer, and a buffer layer under the N-type first semiconductor layer.

8. A semiconductor light emitting device, comprising:

a substrate;

an N-type first semiconductor layer on the substrate;

a light emitting structure on a first area of the N-type first semiconductor layer;

a P-N junction protection device structure on a second area of the N-type first semiconductor layer;

a first electrode layer on the P-N junction protection device structure; and

a second electrode layer on the light emitting structure,

wherein the light emitting structure comprises: an N-type second semiconductor layer on the first area of the N-type first semiconductor layer; an active layer on the N-type second semiconductor layer; and a P-type first semiconductor layer on the active layer,

wherein the P-N junction protection device structure comprises: a P-type second semiconductor layer tunnel functioned on the second area of the N-type first semiconductor layer; and an N-type third semiconductor layer between the first electrode layer and the P-type second semiconductor layer, and

wherein the N-type first semiconductor layer, the P-type second semiconductor layer, and the N-type third semiconductor layer form an N-P-N junction, and when a reverse ESD is applied to the first electrode, the reverse ESD flows and dissipates through the N-P-N junction.

9. The semiconductor light emitting device of claim 8 , wherein the P-N junction protection device structure is connected in inverse-parallel with the light emitting structure.

10. The semiconductor light emitting device of claim 8 , wherein the light emitting structure comprises an N-P-N junction structure.

11. The semiconductor light emitting device of claim 8 , wherein the P-type second semiconductor layer and the N-type third semiconductor layer are formed of at least one selected from the group consisting of GaN, InN, AlN, InGaN, AlGaN, InAlGaN, and AlInN in a superlattice structure.

12. The semiconductor light emitting device of claim 8 , comprising a transparent mask layer on the first area of the P-N junction protection device structure.

13. The semiconductor light emitting device of claim 8 , wherein the P-type second semiconductor layer is formed in a thickness range of 5 Å to 500 Å to form a tunnel junction with the N-type first semiconductor layer.

14. The semiconductor light emitting device of claim 8 , wherein the N-type third semiconductor layer is formed in a thickness range of 10 Å to 3 μm.

15. The semiconductor light emitting device of claim 8 , wherein the light emitting structure connected on the N-type first semiconductor layer separates from the P-N junction protection device structure connected on the N-type first semiconductor layer.

16. The semiconductor light emitting device of claim 8 , wherein the P-type second semiconductor layer and the N-type third semiconductor layer are formed in superlattice structure selected from the group consisting of GaN, InN, MN, InGaN, AlGaN, InAlGaN and AlInN.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 4, 2024
From: SUZHOU LEKIN SEMICONDUCTOR CO., LTD.
To: FAIRLIGHT INNOVATIONS, LLC
Reel/Frame 068839/0745 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 25, 2021
From: LG INNOTEK CO., LTD.
To: SUZHOU LEKIN SEMICONDUCTOR CO., LTD.
Reel/Frame 056366/0335 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 4, 2008
From: LEE, JO YOUNG
To: LG INNOTEK CO., LTD.
Reel/Frame 021483/0874 →
Priority Claims (1)
KR 10-2007-0088286 · Aug 31, 2007 · national
Continuity (1)
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