High speed digital galvanic isolator with integrated low-voltage differential signal interface
View Patent ↗Various types of high-speed digital galvanic isolators and corresponding integrated low voltage differential signal (“LVDS”) interfaces are disclosed herein. According to some embodiments, phantom power is provided to one side of a galvanic isolator from the other side of the isolator via a twisted pair cable with shielding interconnecting the two sides, and therefore eliminate the need to provide power to both sides of the galvanic isolator through different power supplies or by way of separate physical wiring being routed and connected to the two opposing sides of the isolator. Such phantom power supply configurations reduce cost, lower power consumption, and increase the number of engineering design options available in a device where high speed serial data communication with low noise are required.
1. A high-speed digital isolator, comprising:
a transmitter circuit comprising a first low-voltage differential signal (“LVDS”) interface configured to receive input differential data signals;
a receiver circuit comprising a second LVDS interface configured to provide output differential data signals therefrom;
a shielded twisted pair cable (“TPC”) comprising first and second electrical conductors and an electrically conductive shield disposed thereover, the TPC being disposed between the transmitter circuit and the receiver circuit and operably coupled thereto, the TPC further being configured to convey the input differential data signals from the transmitter circuit to the receiver circuit, and to provide phantom power to the transmitter circuit from the receiver circuit, via the first and second electrical conductors and the shield, the TPC having an impedance Z 0 associated therewith;
first and second termination resistors operably coupled to termination ends of the first and second electrical conductors in the transmitter circuit, respectively, each termination resistor having an impedance of about Z 0 /2; and
first and second source resistors operably coupled to source ends of the first and second electrical conductors in the receiver circuit, respectively, each source resistor having an impedance of about Z 0 /2;
wherein the transmitter circuit is configured to provide galvanic isolation between the transmitter circuit and the receiver circuit; and
wherein the transmitter circuit further comprises a voltage regulator configured to regulate power received from the receiver circuit via the TPC.
2. The high-speed digital isolator of claim 1 , wherein the isolator is configured to convey data signals therethrough at a rate exceeding about 100 Mbps.
3. The high-speed digital isolator of claim 1 , wherein the isolator is configured to convey data signals therethrough at a rate between about 500 Mbps and about 3.75 Gbps.
4. The high-speed digital isolator of claim 1 , wherein the TPC has a length exceeding about 0.5 meters, about 1 meter, about 2 meters, about 3 meters, about 4 meters, about 5 meters, about 6 meters, about 7 meters, about 8 meters, about 9 meters, about 10 meters, about 20 meters, about 30 meters or about 50 meter.
5. The high-speed digital isolator of claim 1 , wherein the isolator is further configured to adjust skew between clock and data rates using clock data recovery (“CDR”) techniques.
6. The high-speed digital isolator of claim 1 , wherein the isolator is incorporated into a Media Oriented System Transport (“MOST”) network.
7. The high-speed digital isolator of claim 6 , wherein the MOST network is incorporated into an automobile.
8. The high-speed digital isolator of claim 6 , wherein the MOST network is configured to operate a speed ranging between about 25 Mbps and about 1 Gbps.
9. The high-speed digital isolator of claim 1 , wherein the transmitter circuit is a serializer and the receiver circuit is a deserializer.
10. The high-speed digital isolator of claim 1 , wherein the receiver circuit is an integrated circuit.
11. The high-speed digital isolator of claim 1 , wherein the transmitter circuit is an integrated circuit.
12. A high-speed digital isolator, comprising:
a transmitter circuit comprising a first low-voltage differential signal (“LVDS”) interface configured to receive input differential data signals;
a receiver circuit comprising a second LVDS interface configured to provide output differential data signals therefrom;
a shielded twisted pair cable (“TPC”) comprising first and second electrical conductors and an electrically conductive shield disposed thereover, the TPC being disposed between the transmitter circuit and the receiver circuit and operably coupled thereto, the TPC further being configured to convey the input differential data signals from the transmitter circuit to the receiver circuit, and to provide phantom power to the receiver circuit from the transmitter circuit, via the first and second electrical conductors and the shield, the TPC having an impedance Z 0 associated therewith;
first and second termination resistors operably coupled to termination ends of the first and second electrical conductors in the transmitter circuit, respectively, each termination resistor having an impedance of about Z 0 /2; and
first and second source resistors operably coupled to source ends of the first and second electrical conductors in the receiver circuit, respectively, each source resistor having an impedance of about Z 0 /2;
wherein the receiver circuit is configured to provide galvanic isolation between the transmitter circuit and the receiver circuit; and
wherein the receiver circuit further comprises a voltage regulator configured to regulate power received from the transmitter circuit via the TPC.
13. The high-speed digital isolator of claim 12 , wherein the isolator is configured to convey data signals therethrough at a rate exceeding about 100 Mbps.
14. The high-speed digital isolator of claim 12 , wherein the isolator is configured to convey data signals therethrough at a rate between about 500 Mbps and about 3.75 Gbps.
15. The high-speed digital isolator of claim 12 , wherein the TPC has a length exceeding about 0.5 meters, about 1 meter, about 2 meters, about 3 meters, about 4 meters, about 5 meters, about 6 meters, about 7 meters, about 8 meters, about 9 meters, about 10 meters, about 20 meters, about 30 meters or about 50 meters.
16. The high-speed digital isolator of claim 12 , wherein the isolator is further configured to adjust skew between clock and data rates using clock data recovery (“CDR”) techniques.
17. The high-speed digital isolator of claim 12 , wherein the transmitter circuit is a serializer and the receiver circuit is a deserializer.
18. The high-speed digital isolator of claim 12 , wherein the isolator is incorporated into a Media Oriented System Transport (“MOST”) network.
19. The high-speed digital isolator of claim 18 , wherein the MOST network is incorporated into an automobile.
20. The high-speed digital isolator of claim 18 , wherein the MOST network is configured to operate a speed ranging between about 25 Mbps and about 1 Gbps.
21. The high-speed digital isolator of claim 12 , wherein the transmitter circuit is an integrated circuit.
22. The high-speed digital isolator of claim 12 , wherein the receiver circuit is an integrated circuit.
23. A high-speed digital transmitter, comprising:
a low-voltage differential signal (“LVDS”) interface configured to receive input differential data signals therethrough;
a transmitter circuit operably coupled to the LVDS interface and configured to transmit the differential data signals therefrom;
a shielded twisted pair cable (“TPC”) comprising first and second electrical conductors and an electrically conductive shield disposed thereover, the TPC being operably connected to the transmitter circuit to convey the differential data signals therethrough and to provide phantom power to the transmitter circuit from an external source via the first and second electrical conductors and the shield, the TPC having an impedance Z 0 associated therewith; and
first and second termination resistors operably coupled to termination ends of the first and second electrical conductors in the transmitter circuit, respectively, each termination resistor having an impedance of about Z 0 /2;
wherein the high-speed digital transmitter is configured to provide galvanic isolation between the transmitter circuit and a receiver circuit; and
wherein the transmitter circuit comprises a voltage regulator configured to regulate power received via the TPC.
24. The high-speed digital transmitter of claim 23 , wherein the transmitter circuit is incorporated into an integrated circuit.
25. The high-speed digital transmitter of claim 23 , wherein the external source is the receiver circuit.
26. A high-speed digital receiver, comprising:
a low-voltage differential signal (“LVDS”) interface configured to provide output differential data signals therefrom;
a receiver circuit operably coupled to the LVDS interface and configured to convey the differential data signals thereto;
a shielded twisted pair cable (“TPC”) comprising first and second electrical conductors and an electrically conductive shield disposed thereover, the TPC being operably connected to the receiver circuit to convey the differential data signals thereto from a transmitter circuit and to provide phantom power to the receiver circuit from an external source via the first and second electrical conductors and the shield, the TPC having an impedance Z 0 associated therewith; and
first and second source resistors operably coupled to source ends of the first and second electrical conductors in the receiver circuit, respectively, each source resistor having an impedance of about Z 0 /2;
wherein the high-speed digital receiver is configured to provide galvanic isolation between the receiver circuit and the transmitter circuit; and
wherein the receiver circuit comprises a voltage regulator configured to regulate power received from the transmitter circuit via the TPC.
27. The high-speed digital receiver of claim 26 , wherein the receiver circuit is incorporated into an integrated circuit.
28. The high-speed digital transmitter of claim 26 , wherein the external source is the transmitter circuit.
29. A high-speed digital transceiver, comprising:
a transmitter circuit comprising a first low-voltage differential signal (“LVDS”) interface configured to receive first differential data signals;
a receiver circuit comprising a second LVDS interface configured to receive second differential data signals;
first and second shielded twisted pair cables (“TPCs”), each TPC comprising first and second electrical conductors and an electrically conductive shield disposed thereover, the first TPC being operably coupled to outputs of the transmitter circuit, the second TPC being operably coupled to inputs of the receiver circuit, each TPC further being configured to convey differential data signals therethrough and to provide phantom power to the transmitter and receiver circuits, respectively, from external sources; and
at least one voltage regulator configured to regulate power received via the first or second TPC;
wherein the transmitter and receiver circuits are configured to provide galvanic isolation in respect of circuits external to the transceiver.
30. The high-speed digital transceiver of claim 29 , wherein the receiver and transmitter circuits are incorporated into at least one integrated circuit.