Granted Patent B2

US 7,921,317 · App. 12/202,724 · Granted Apr 5, 2011

Abstract

Claims (46)

1. A method comprising:

repeatedly performing, by a processor synchronization device coupled to a plurality of central processing units (CPUs), timing update operations that include:

selecting one of the plurality of CPUs;

determining a reference time;

utilizing an offset table indexed by processor identifiers to determine an offset value estimating a delay time to process a timer update at the selected CPU;

causing the plurality of CPUs to write current counter values to the respective cache lines of the CPUs;

determining the values of the offset table by comparing the current counter values to the reference time;

determining a corrected timer value of the selected CPU based on the offset value and the reference time;

writing the corrected timer value to a cache line of the selected CPU; and

causing the selected CPU to update the timer of the selected CPU based on the corrected timer value written to the cache line.

2. The method of claim 1 , wherein the offset value comprises a time required to write the corrected timer value to the cache line of the selected CPU and a CPU processing time to update the timer of the selected CPU.

3. The method of claim 1 , wherein causing the selected CPU to update the timer of the selected CPU comprises sending an interrupt to the selected CPU, wherein an interrupt handler of the selected CPU causes the selected CPU to update the timer of the selected CPU based on the corrected timer value of the cache line.

4. The method of claim 1 , further comprising determining update time intervals that are unique to each of the plurality of CPUs, and wherein the one of the plurality of CPUs is selected based on the update time interval associated with the selected CPU.

5. The method of claim 1 , further comprising storing the corrected timer value in a register of the synchronization device, wherein the register modifies the corrected timer value to maintain correspondence with the reference time to account for delays in writing the corrected timer value to the cache line of the selected CPU.

6. An apparatus, comprising:

a memory interface capable of communicating with a plurality of central processing units (CPUs) via at least one memory bus;

an offset table comprising a plurality of offset values that each estimate a delay time to process a timer update at respective ones of the central processing units;

a master counter that determines a reference time;

an update controller logic circuit coupled to the offset table and the master counter, wherein the update controller performs update operations that include:

determining corrected timer values for the central processing units based on the reference time and the offset values;

writing, via the memory interface, the corrected timer values to cache lines of the respective central processing units; and

causing the central processing units to update their timers based on the corrected timer values written to the cache lines.

7. The apparatus according to claim 6 , and further comprising a setup controller that performs setup operations comprising:

causing the plurality of central processing units to write current counter values to the respective cache lines of the central processing units; and

determining the values of the offset table by comparing the current counter values to the reference time.

8. The apparatus according to claim 6 , wherein the offset values comprise times required to write the corrected timer value to the respective cache lines of the central processing units and central processing unit processing times to update the respective timers of the central processing units.

9. The apparatus according to claim 6 , and further comprising an interrupt/address table coupled to the update controller and the memory interface, the interrupt/address table comprising addresses and associated interrupt vectors for each of the central processing units, and wherein causing the central processing units to update their timers comprises sending interrupts to the respective central processing units via the interrupt/address table, and wherein interrupt handlers of the respective central processing units cause the respective central processing units to update their timers in response to the interrupts.

10. The apparatus according to claim 9 , wherein the interrupt/address table and the offset table are indexed by a processor identifier, and wherein the update operations are initiated by the update controller sending a processor select signal to the interrupt/address table and the offset table.

11. The apparatus according to claim 6 , wherein the update operations further comprise determining update time intervals unique to each of the plurality of CPUs, and wherein a selected one of the plurality of CPUs is selected based on the update time interval associated with the selected CPU.

12. The apparatus according to claim 6 , further comprising an adder coupled to the master counter, the offset table, and the memory interface, wherein the adder determines the corrected timer values by summing the reference time and the offset values, and wherein the adder writes the corrected timer values to the memory interface in response to the summing operation.

13. The apparatus according to claim 12 , further comprising a counter-type register that couples the adder to the memory interface, wherein the counter type register causes the corrected timer values to maintain correspondence with the master counter to account for delays in writing the corrected timer values via the memory interface.

14. The apparatus according to claim 6 , wherein the memory interface comprises a peripheral input-output interface.

15. The apparatus according to claim 6 , wherein the memory interface comprises a front-side bus interface.

16. The apparatus of claim 6 , wherein the master counter comprises an interface to an external reference time source, and wherein the master counter is updated by the external reference time source.

17. An apparatus, comprising:

means for interfacing with a plurality of central processing units;

means for determining corrected timer values for each of the central processing units as a function of predetermined values indexed by processor identifiers;

means for causing the plurality of central processing units to write current counter values to the respective cache lines of the central processing units; and

means for determining offset values of each of the central processing units based on the current counter values, wherein each of the offset values estimate a delay time to update counters of respective ones of the central processing units;

means for writing the corrected timer values to cache lines of the respective central processing units; and

means for causing the central processing units to update their timers based on the corrected timer values written to the cache lines.

18. The apparatus of claim 17 , further comprising

means for causing the plurality of central processing units to write current counter values to the respective cache lines of the central processing units; and

means for determining offset values of each of the central processing units based on the current counter values, wherein each of the offset values estimate a delay time to update counters of respective ones of the central processing units.

19. The apparatus of claim 17 , further comprising

means for causing the corrected timer values to maintain correspondence with a master counter reference time before the corrected timer values are written to the cache lines to account for delays in writing the corrected timer values to the cache lines.

Assignments (13)