Switched capacitor measurement circuit for measuring the capacitance of an input capacitor

1. A switched capacitor measurement circuit for measuring the capacitance of an input capacitor (CIN) with a parallel parasitic resistor (RPAR), comprising:

a switching arrangement (S 1 , S 2 . . . S 5 ), a reference capacitor (CREF);

a steered current sink (IDAC) and an operational amplifier (OP) with an output;

a non-inverting input connected to a reference voltage source (VREF) and an inverting input connected to a first terminal of the input capacitor (CIN), said switching arrangement selectively connecting:

in a reset mode, a second terminal of said input capacitor (CIN) with the reference voltage source (VREF), the inverting input of the operational amplifier (OP) with the output of the operational amplifier, and the reference capacitor (CREF) between the reference voltage source (VREF) and the inverting input of the operational amplifier (OP);

in a gain mode, the second terminal of said input capacitor (CIN) with a supply voltage (VDD), the reference capacitor (CREF) between the inverting input and the output of the operational amplifier (OP), and the steered current sink (IDAC) with an interconnection node between the input capacitor (CIN) and the reference capacitor (CREF);

wherein the current sink (IDAC) is steered by a control loop to compensate for a charge current due to the parasitic resistor (RPAR).

2. The switched capacitor measurement circuit of claim 1 further comprising a digital adder (DADD) and an analog-to-digital converter (ADC) with an analog input connected to the output of the operational amplifier (OP) and a digital output (DOUT) connected to a first input of the digital adder (DADD), a second input of the digital adder receiving a negative digital error signal (DERROR) and the output of the digital adder (DADD) providing a digital capacitance measurement signal (DOUT-CORR) corrected for an error current which is integrated across the reference capacitor (CREF) in the gain mode due to the slewing of the operational amplifier (OP).

3. The switched capacitor measurement circuit according to claim 2 , wherein the current sink (IDAC) is steered by a control loop to compensate for a current of (VDD−VREF)/RPAR, wherein

VDD is the input voltage from the supply voltage source,

VREF is the reference voltage and

RPAR is the resistance of the parasitic resistor.

4. The switched capacitor measurement circuit according to claim 3 , wherein the digital error signal (DERROR) is determined by the formula:

DERROR =−IDAC/(2*IOTA)*DOUT

wherein

DERROR is the digital error signal,

IDAC is the current that flows to the current sink in gain mode,

IOTA is the slewing current supplied from the output of the operational amplifier,

DOUT is the digitalized output voltage of the operational amplifier.

5. The switched capacitor measurement circuit according to claim 4 , wherein the operational amplifier (OP) is a transconductance amplifier.

6. The switched capacitor measurement circuit according to claim 3 , wherein the operational amplifier (OP) is a transconductance amplifier.

7. The switched capacitor measurement circuit according to claim 2 , wherein the digital error signal (DERROR) is determined by the formula:

DERROR=−IDAC/(2*IOTA)*DOUT

wherein

DERROR is the digital error signal,

IDAC is the current that flows to the current sink in gain mode,

IOTA is the slewing current supplied from the output of the operational amplifier,

DOUT is the digitalized output voltage of the operational amplifier.

8. The switched capacitor measurement circuit according to claim 7 , wherein the operational amplifier (OP) is a transconductance amplifier.

9. The switched capacitor measurement circuit according to claim 2 , wherein the digital error signal (DERROR) is determined by the formula:

DERROR =−IDAC/(2*IOTA)*DOUT

wherein

DERROR is the digital error signal,

IDAC is the current that flows to the current sink in gain mode,

IOTA is the slewing current supplied from the output of the operational amplifier,

DOUT is the digitalized output voltage of the operational amplifier.

10. The switched capacitor measurement circuit according to claim 2 , wherein the operational amplifier (OP) is a transconductance amplifier.

11. The switched capacitor measurement circuit according to claim 1 , wherein the current sink (IDAC) is steered by a control loop to compensate for a current of (VDD−VREF)/RPAR, wherein

VDD is the input voltage from the supply voltage source,

VREF is the reference voltage and

RPAR is the resistance of the parasitic resistor.

12. The switched capacitor measurement circuit according to claim 11 , wherein the digital error signal (DERROR) is determined by the formula:

DERROR=−IDAC/(2*IOTA)*DOUT

wherein

DERROR is the digital error signal,

IDAC is the current that flows to the current sink in gain mode,

IOTA is the slewing current supplied from the output of the operational amplifier,

DOUT is the digitalized output voltage of the operational amplifier.

13. The switched capacitor measurement circuit according to claim 12 , wherein the operational amplifier (OP) is a transconductance amplifier.

14. The switched capacitor measurement circuit according to claim 11 , wherein the operational amplifier (OP) is a transconductance amplifier.

15. The switched capacitor measurement circuit according to claim 1 , wherein the operational amplifier (OP) is a transconductance amplifier.

16. A method of switched capacitor measurement circuit for measuring the capacitance of an input capacitor (CIN) with a parallel parasitic resistor (RPAR), comprising:

in a first mode, coupling a second terminal of said input capacitor (CIN) with a reference voltage source (VREF);

coupling the inverting input of an operational amplifier (OP) with an output of the operational amplifier; and

coupling a reference capacitor (CREF) between a reference voltage source (VREF) and an inverting input of the operational amplifier (OP); and

in a second mode, coupling a second terminal of said input capacitor (CIN) with a supply voltage (VDD);

coupling the reference capacitor (CREF) between the inverting input and the output of the operational amplifier (OP); and

coupling a steered current sink (IDAC) with an interconnection node between the input capacitor (CIN) and the reference capacitor (CREF);

wherein the current sink (IDAC) is steered to compensate for a charge current due to the parasitic resistor (RPAR).

17. The method of switched capacitor measurement of claim 16 , further comprising:

coupling a digital adder (DADD) and an analog-to-digital converter (ADC) with an analog input connected to the output of the operational amplifier (OP) and a digital output (DOUT) connected to a first input of the digital adder (DADD),

coupling a second input of the digital adder for receiving a negative digital error signal (DERROR) and

wherein the output of the digital adder (DADD) providing a digital capacitance measurement signal (DOUT-CORR) corrected for an error current which is integrated across the reference capacitor (CREF) in the second mode due to the slewing of the operational amplifier (OP).

18. The method of switched capacitor measurement according to claim 17 , wherein the first mode is a reset mode and the second mode is a gain mode.

19. The method of switched capacitor measurement according to claim 16 , wherein the first mode is a reset mode and the second mode is a gain mode.