Data flow control and bridging architecture enhancing performance of removable data storage systems
View Patent ↗A data flow control and bridging architecture that enhances the performance of removable data storage systems. In one implementation, the present invention provides a bypass bus implementation where the data transfer phase associated with select commands occurs directly between the host computing system and the target removable data storage unit. In one implementation, the present invention further provides a data flow and bridging architecture that emulates a removable media interface, such as the ATAPI interface, to the host computing system, and translates these commands for a target removable storage unit that implements a fixed media interface, such as the ATA interface. In yet another implementation, the present invention provides a data flow and bridging architecture that supports the serial ATA interface.
1. An apparatus comprising
a first serial-to-parallel interface bridge that presents a serial data storage device mode interface to a data storage host adapter;
a second serial-to-parallel interface bridge that presents a serial host mode interface to a data storage unit;
a data flow control circuit operably connected to the first serial-to-parallel interface bridge and the second serial-to-parallel interface bridge, wherein the data flow control circuit comprises a task file register;
a controller unit, operably connected to the data flow control circuit, the task file register, and the second serial-to-parallel interface bridge, the controller unit comprising a processor and a command data buffer;
wherein the data flow control circuit is operative to write a first data transfer command received on the task file register from the data storage host adapter to the command data buffer;
wherein the controller unit is further operable to access executable instructions physically stored in a memory and, when executed, operable to cause the processor to
access the first data transfer command stored in the command data buffer;
generate a second data transfer command in the command data buffer corresponding to the first data transfer command; and
transmit the second data transfer command to the data storage unit through the second serial-to-parallel interface bridge; and
wherein the data flow control circuit, responsive to control signals provided by the controller unit, is further operative to directly interface data transfer signals of the data storage host adapter and the data storage unit via the first serial-to-parallel interface bridge and the second serial-to-parallel interface bridge.
2. The apparatus of claim 1 wherein the first data transfer command is embodied in a packet.
3. The apparatus of claim 1 wherein the first serial-to-parallel interface bridge is operative to map serial signals received from the data storage host adapter as parallel signals on the task file register.
4. The apparatus of claim 1 wherein the data flow control circuit, to directly interface data transfer signals, is operative to patch status signals between the data storage host adapter and the data storage unit.
5. The apparatus of claim 1 wherein the data flow control circuit is further operative to write a third command received on the task file register from the data storage host adapter to the command data buffer;
wherein the controller unit is further operable to access executable instructions physically stored in a memory and, when executed, operable to cause the processor to
access the third data transfer command stored in the command data buffer;
generate a fourth command in the command data buffer corresponding to the third command; and
transmit the fourth command to the data storage unit through the second serial-to-parallel interface bridge;
receive data from the data storage unit in response to the fourth command;
generate a response including the data received from the data storage unit; and
access the task file register to transmit the response to the data storage host adapter via the first serial-to-parallel interface bridge.
6. The apparatus of claim 1 further comprising a machine state register indicating status of command execution, wherein the data flow control circuit and the controller unit are responsive to the status indicated by the machine state register.
7. The apparatus of claim 6 wherein the data flow control circuit and the controller unit are both operative to write to, and read, the machine state register.
8. The apparatus of claim 1 wherein the command data buffer comprises one or more first-in-first-out (FIFO) queues.
9. The apparatus of claim 1 wherein the data flow control circuit, responsive to the control signals, directly passes at least one register signal of the first serial-to-parallel interface bridge to at least one register signal of the second serial-to-parallel interface bridge.
10. An apparatus comprising
a first serial-to-parallel interface bridge that presents a serial data storage device mode interface to a data storage host adapter;
a second serial-to-parallel interface bridge that presents a serial host mode interface to a data storage unit;
a data flow control circuit operably connected to the first serial-to-parallel interface bridge and the second serial-to-parallel interface bridge, wherein the data flow control circuit comprises a task file register;
a controller unit, operably connected to the data flow control circuit, the task file register, and the second serial-to-parallel interface bridge, the controller unit comprising a processor and a command data buffer;
wherein the data flow control circuit is operative to write a first data transfer command received on the task file register from the data storage host adapter to the command data buffer;
wherein the controller unit is further operable to access executable instructions physically stored in a memory and, when executed, operable to cause the processor to
access the first data transfer command stored in the command data buffer;
generate a second data transfer command in the command data buffer corresponding to the first data transfer command; and
transmit the second data transfer command to the data storage unit through the second serial-to-parallel interface bridge; and
wherein the data flow control circuit is further operative to directly interface, responsive to control signals provided by the controller unit, the data storage host adapter and the data storage unit for transmission of data via the task file register, the first serial-to-parallel interface bridge and the second serial-to-parallel interface bridge.
11. The apparatus of claim 10 wherein the data flow control circuit is further operative to write a third command received on the task file register from the data storage host adapter to the command data buffer;
wherein the controller unit is further operable to access executable instructions physically stored in a memory and, when executed, operable to cause the processor to
access the third data transfer command stored in the command data buffer;
generate a fourth command in the command data buffer corresponding to the third command; and
transmit the fourth command to the data storage unit through the second serial-to-parallel interface bridge;
receive data from the data storage unit in response to the fourth command;
generate a response including the data received from the data storage unit; and
access the task file register to transmit the response to the data storage host adapter via the first serial-to-parallel interface bridge.
12. The apparatus of claim 10 wherein the first data transfer command is embodied in a packet.
13. The apparatus of claim 10 wherein the first serial-to-parallel interface bridge is operative to map serial signals received from the data storage host adapter as parallel signals on the task file register.
14. The apparatus of claim 10 wherein the data flow control circuit, to directly interface data transfer signals, is operative to patch status signals between the data storage host adapter and the data storage unit.
15. The apparatus of claim 10 further comprising a machine state register indicating status of command execution, wherein the data flow control circuit and the controller unit are responsive to the status indicated by the machine state register.
16. The apparatus of claim 15 wherein the data flow control circuit and the controller unit are both operative to write to, and read, the machine state register.
17. The apparatus of claim 10 wherein the command data buffer comprises one or more first-in-first-out (FIFO) queues.
18. The apparatus of claim 10 wherein the data flow control circuit, responsive to the control signals, directly passes at least one register signal of the first serial-to-parallel interface bridge to at least one register signal of the second serial-to-parallel interface bridge.
19. An apparatus comprising
a first serial-to-parallel interface bridge that presents a serial data storage device mode interface to a data storage host adapter;
a second serial-to-parallel interface bridge that presents a serial host mode interface to a data storage unit;
a data flow control circuit operably connected to the first serial-to-parallel interface bridge and the second serial-to-parallel interface bridge, wherein the data flow control circuit comprises a task file register;
a controller unit, operably connected to the data flow control circuit, the task file register, and the second serial-to-parallel interface bridge, the controller unit comprising a processor and a command data buffer;
wherein the data flow control circuit is operative to
write a first command received on the task file register from the data storage host adapter to the command data buffer, and
directly interface, responsive to control signals provided by the controller unit, the data storage host adapter and the data storage unit for transmission of data via the task file register, the first serial-to-parallel interface bridge and the second serial-to-parallel interface bridge;
wherein the controller unit is further operable to access executable instructions physically stored in a memory and, when executed, operable to cause the processor to
access the first command stored in the command data buffer to determine whether the first command is a direct or indirect data transfer command;
generate a second data transfer command in the command data buffer corresponding to the first data transfer command;
transmit the second data transfer command to the data storage unit through the second serial-to-parallel interface bridge; and
transmit, if the first command is a direct data transfer command, control signals operative to cause the data flow control circuit to directly interface the data storage host adapter and the data storage unit for transmission of data.
20. The apparatus of claim 19 wherein the data flow control circuit, responsive to the control signals, directly passes at least one register signal of the first serial-to-parallel interface bridge to at least one register signal of the second serial-to-parallel interface bridge.