IP Library Granted Patent US 7,858,272
Granted Patent B2
US 7,858,272 · App. 12/206,592 · Granted Dec 28, 2010

Exposure mask and method for fabricating thin-film transistor

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Quick Facts
Patent No.
US 7,858,272
App. No.
12/206,592
Granted
Dec 28, 2010
Kind
B2
Abstract

An exposure mask includes a transparent substrate; a first pattern portion formed on the transparent substrate using at least one light-shielding pattern having a predetermined shape; and a translucent layer which is formed at a section including a first pattern region having the first pattern portion, which allows exposure light to pass therethrough, and which has a transmittance greater than that of the light-shielding pattern.

Claims (26)

1. An exposure mask comprising:

a transparent substrate;

a first pattern portion formed on the transparent substrate including at least one light-shielding pattern having a predetermined shape; and

a translucent layer which is formed at a section including a first pattern region having the first pattern portion, which allows exposure light to pass therethrough, and which has a transmittance greater than that of the light-shielding pattern, wherein

the translucent layer has an extending portion extending from a portion which is disposed on the transparent substrate and which overlaps with a region having the light-shielding pattern to at least one portion of a region which is disposed on the transparent substrate and which has no light-shielding pattern,

the light-shielding pattern has a second pattern portion which is different from the first pattern portion and which is located at a second pattern region which is different from the first pattern region and which is disposed on the transparent substrate, the first and second portions having a transmittance, and

the transmittance of the second pattern portion is less than a transmittance of the first pattern portion, and the transmittance of the first pattern portion is less than the transmittance of a third region disposed on the transparent substrate with no light-shielding pattern.

2. The exposure mask according to claim 1 , wherein the first pattern portion corresponds to a striped or dotted repeating portion of the light-shielding pattern.

3. The exposure mask according to claim 1 , wherein the area ratio of the second pattern portion to the second pattern region is greater than the area ratio of the first pattern portion to the first pattern region.

4. The exposure mask according to claim 1 , wherein the second pattern portion extends over the second pattern region.

5. A method for fabricating a thin-film transistor, comprising:

forming a gradient resist film by exposing a resist layer disposed on a semiconductor layer to exposure light through the exposure mask according to claim 1 ; and

implanting impurity ions into the semiconductor layer through the gradient resist film.

6. The method according to claim 5 , further comprising etching the semiconductor layer using the gradient resist film.

7. A method for fabricating a thin-film transistor, comprising:

forming a gradient resist film by exposing a resist layer disposed on a semiconductor layer to exposure light through the exposure mask according to claim 3 ; and

implanting impurity ions into the semiconductor layer through the gradient resist film.

8. A method for fabricating a thin-film transistor, comprising:

forming a gradient resist film by exposing a resist layer disposed on a semiconductor layer to exposure light through the exposure mask according to claim 4 ; and

implanting impurity ions into the semiconductor layer through the gradient resist film.

9. A method for fabricating a thin-film transistor, comprising:

forming a gradient resist film by exposing a resist layer disposed on a semiconductor layer to exposure light through the exposure mask according to claim 2 ; and

implanting impurity ions into the semiconductor layer through the gradient resist film.

10. The exposure mask according to claim 1 , further comprising:

a plurality of first pattern portions, and

a plurality of extending portions.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 15, 2018
From: SEIKO EPSON CORPORATION
To: 138 EAST LCD ADVANCEMENTS LIMITED
Reel/Frame 046153/0397 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 8, 2008
From: MIYATA, TAKASHI
To: SEIKO EPSON CORPORATION
Reel/Frame 021503/0741 →