Circuit for data synchronization of I2C time controller in display device and method thereof

1. A method of controlling an interface between an I2C master in a time controller for a liquid crystal display and an external memory, the method comprising:

determining whether a first clock signal transmitted by the I2C master to the external memory is synchronized with a second clock signal transmitted by the external memory to the I2C master using a pre-scaler; and then

preventing transmission of a third clock signal using the pre-scaler for an I2C interface with the external memory to the I2C master when the first clock signal is not synchronized with the second clock signal.

2. The method of claim 1 , wherein the second clock signal is transmitted from the external memory to the I2C master through a noise filter such that noise is removed therefrom.

3. The method of claim 1 , wherein a tolerance of time delay for synchronization determination is provided between the first clock signal and the second clock signal.

4. The method of claim 3 , wherein the tolerance of time delay is an integer multiple of an external clock for controlling the operation of the time controller.

5. The method of claim 1 , wherein determining whether the first clock signal is synchronized with the second clock signal comprises:

determining whether the first clock signal and the second clock signal are in a high state or a low state.

6. The method of claim 1 , wherein the external memory comprises an EEPROM.

7. A time controller for a liquid crystal display connected to an external memory, the time controller comprising:

an I2C master that performs an I2C interface with the external memory; and

a pre-scaler connected to a transmission path for a first clock signal from the I2C master to the external memory and a transmission path for a second clock signal from the external memory to the I2C master, the pre-scaler transmitting a third clock signal for the I2C interface with the external memory to the I2C master, wherein the pre-scaler determines whether the first clock signal is synchronized with the second clock signal.

8. The time controller of claim 7 , further comprising:

a noise filter provided between the external memory and the I2C master to remove noise from the second clock signal.

9. The time controller of claim 7 , wherein the external memory comprises an EEPROM.

10. A method of controlling an interface between an I2C master in a time controller for a liquid crystal display and an external memory, the method comprising:

transmitting a first clock signal and a first data transmission signal from an I2C master to an external memory;

transmitting a second clock signal and a second data transmission signal from the external memory to the I2C master, wherein noise is removed from a second clock signal and a second data transmission signal before the second clock signal is input to the I2C master;

providing a pre-scaler between the external memory and the I2C master in a transmission path of the first clock signal and the second clock signal;

comparing the first clock signal and the second clock signal; and then

establishing an I2C interface between the I2C master and the external memory if, after comparing the first clock signal and the second clock signal, the first clock signal is synchronized with the second clock signal.

11. The method of claim 10 , wherein establishing an I2C interface between the I2C master and the external memory comprises:

transmitting, after comparing the first clock signal and the second clock signal, a third clock signal to the I2C master using the pre-scaler if the first signal is synchronized with the second clock signal.

12. The method of claim 11 , wherein comparing the first clock signal and the second clock signal is performed using the pre-scaler.

13. The method of claim 12 , wherein determining whether the first clock signal is synchronized with the second clock signal comprises:

determining whether the first clock signal and the second clock signal are in a high state or a low state.

14. The method of claim 10 , wherein comparing the first clock signal and the second clock signal comprises:

determining whether the first clock signal is synchronized with the second clock signal.

15. The method of claim 14 , wherein determining whether the first clock signal is synchronized with the second clock signal comprises:

determining whether the first clock signal and the second clock signal are in a high state or a low state.

16. The method of claim 10 , wherein establishing an I2C interface between the I2C master and the external memory comprises:

determining whether the first clock signal and the second clock signal are in a high state or a low state.

17. The method of claim 10 , wherein the external memory comprises an EEPROM.

18. The method of claim 10 , further comprising, after comparing the first clock signal and the second clock signal:

preventing the establishment of an I2C interface between the I2C master and the external memory if the first clock signal is not synchronized with the second clock signal.

19. The method of claim 18 , wherein preventing the establishment of an I2C interface between the I2C master and the external memory comprises:

preventing transmission, after comparing the first clock signal and the second clock signal, of a third clock signal from the pre-scaler to the I2C master if the first signal is not synchronized with the second clock signal.

20. The method of claim 10 , wherein a tolerance of time delay for determining whether the first clock signal is synchronized with the second clock signal is provided between the first clock signal and the second clock signal, the tolerance of time delay being an integer multiple of an external clock for controlling the operation of the time controller.