Ultra-violet protected tamper resistant embedded EEPROM
View Patent ↗A pre-metal dielectric structure of a single-poly EEPROM structure includes a UV light-absorbing film, which prevents the charge on a floating gate of the EEPROM structure from being changed in response to UV radiation. In one embodiment, the pre-metal dielectric structure includes a first pre-metal dielectric layer, an amorphous silicon layer located over the first pre-metal dielectric layer, and a second pre-metal dielectric layer located over the amorphous silicon layer.
1. A method of fabricating a semiconductor device, comprising:
forming a single conductive gate layer over a surface of a semiconductor region;
patterning the single conductive gate layer to create a plurality of gate structures, including one or more floating gates, and a control gate adjacent to each of the one or more floating gates;
forming a first dielectric layer over the gate structures and the semiconductor region;
forming an amorphous silicon layer over the first dielectric layer; and
forming a second dielectric layer over the amorphous silicon layer.
2. The method of claim 1 , wherein each of the one or more floating gates and the adjacent control gate form a portion of an associated electrically erasable and programmable read only memory (EEPROM) cell.
3. The method of claim 1 , wherein the step of forming the single conductive gate layer comprises depositing a layer of polycrystalline silicon.
4. The method of claim 1 , further comprising:
forming a plurality of contact openings through the first dielectric layer, the amorphous silicon layer and the second dielectric layer; and
forming electrically conductive contacts in the contact openings.
5. The method of claim 4 , wherein the step of forming the electrically conductive contacts comprises forming the electrically conductive contacts in contact with the amorphous silicon layer.
6. The method of claim 4 , further comprising forming a first dielectric region at locations where the amorphous silicon layer is exposed by the contact openings.
7. The method of claim 6 , further comprising forming the first dielectric region by in-situ steam generation (ISSG).
8. The method of claim 6 , further comprising forming the first dielectric region by chemical vapor deposition (CVD).
9. The method of claim 8 , wherein the first dielectric region comprises tetra-ethoxy-silane (TEOS).
10. The method of claim 6 , further comprising forming a second dielectric region over the first dielectric region, wherein the first and second dielectric regions have different compositions.
11. The method of claim 4 , further comprising forming a patterned first metal layer over the second dielectric layer and in contact with the electrically conductive contacts.
12. The method of claim 11 , wherein the step of forming the electrically conductive contacts comprises contacting the semiconductor region.
13. The method of claim 11 , further comprising forming a patterned second metal layer over the patterned first metal layer, wherein the electrically conductive contacts contact the patterned first and second metal layers.
14. The method of claim 1 , further comprising forming the first dielectric layer, the amorphous silicon layer and the second dielectric layer such that the amorphous silicon layer is in contact with the first dielectric layer and the second dielectric layer.
15. The method of claim 1 , further comprising forming a first diffusion barrier layer between the first dielectric layer and the amorphous silicon layer.
16. The method of claim 15 , further comprising forming a second diffusion barrier layer between the second dielectric layer and the amorphous silicon layer.