High performance system-on-chip using post passivation process
The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface.
1 . An integrated circuit chip comprising:
a silicon substrate;
multiple semiconductor devices in or on said silicon substrate, wherein said multiple semiconductor devices comprise a transistor in or on said silicon substrate;
a first dielectric layer over said silicon substrate;
a metallization structure over said first dielectric layer, wherein said metallization structure is connected to said multiple semiconductor devices, and wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer;
a second dielectric layer between said first and second metal layers;
a passivation layer over said metallization structure and over said first and second dielectric layers;
a ferromagnetic layer over said passivation layer;
a first polymer layer over said passivation layer and over said ferromagnetic layer, wherein said first polymer layer has a thickness between 2 and 150 micrometers and greater than that of said passivation layer, that of said first dielectric layer and that of said second dielectric layer;
a coil on said first polymer layer, over said passivation layer and over said ferromagnetic layer, wherein said coil comprises electroplated copper, and wherein said coil has a thickness greater than that of said first metal layer and that of said second metal layer;
a metal line on said first polymer layer and over said passivation layer, wherein said metal line has a thickness greater than that of said first metal layer and that of said second metal layer, and wherein said metal line and said coil are disconnected from each other; and
a second polymer layer over said metal line.
2 . The integrated circuit chip of claim 1 , wherein said passivation layer comprises a nitride layer.
3 . The integrated circuit chip of claim 1 , wherein said passivation layer comprises a nitride layer having a thickness between 0.5 and 2 micrometers.
4 . The integrated circuit chip of claim 1 , wherein said first polymer layer comprises polyimide.
5 . The integrated circuit chip of claim 1 , wherein said first polymer layer comprises benzocyclobutene (BCB).
6 . The integrated circuit chip of claim 1 , wherein said passivation layer comprises an oxide layer and a nitride layer over said oxide layer.
7 . The integrated circuit chip of claim 1 , wherein said metallization structure comprises electroplated copper.
8 . An integrated circuit chip comprising:
a silicon substrate;
multiple semiconductor devices in or on said silicon substrate, wherein said multiple semiconductor devices comprise a transistor in or on said silicon substrate;
a first dielectric layer over said silicon substrate;
a metallization structure over said first dielectric layer, wherein said metallization structure is connected to said multiple semiconductor devices, and wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer;
a second dielectric layer between said first and second metal layers;
a passivation layer over said metallization structure and over said first and second dielectric layers;
a ferromagnetic layer over said passivation layer;
a polymer layer on said passivation layer and over said ferromagnetic layer; and
a coil on said polymer layer, over said passivation layer and over said ferromagnetic layer, wherein said coil comprises an electroplated metal layer, and wherein said coil has a thickness greater than that of said first metal layer and that of said second metal layer.
9 . The integrated circuit chip of claim 8 , wherein said electroplated metal layer comprises electroplated gold.
10 . The integrated circuit chip of claim 8 , wherein said electroplated metal layer comprises electroplated copper.
11 . The integrated circuit chip of claim 8 , wherein said polymer layer comprises polyimide.
12 . The integrated circuit chip of claim 8 , wherein said polymer layer comprises benzocyclobutene (BCB).
13 . The integrated circuit chip of claim 8 , wherein said passivation layer comprises an oxide layer and a nitride layer over said oxide layer.
14 . The integrated circuit chip of claim 8 , wherein said metallization structure comprises electroplated copper.
15 . An integrated circuit chip comprising:
a silicon substrate;
multiple semiconductor devices in or on said silicon substrate, wherein said multiple semiconductor devices comprise a transistor in or on said silicon substrate;
a first dielectric layer over said silicon substrate;
a metallization structure over said first dielectric layer, wherein said metallization structure is connected to said multiple semiconductor devices, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said metallization structure comprises electroplated copper;
a second dielectric layer between said first and second metal layers;
a passivation layer over said metallization structure and over said first and second dielectric layers, wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip;
a ferromagnetic layer over said passivation layer;
an insulating layer on said passivation layer and over said ferromagnetic layer; and
a coil on said insulating layer, over said passivation layer and over said ferromagnetic layer, wherein said coil comprises an electroplated metal layer, and wherein said coil has a thickness greater than that of said first metal layer and that of said second metal layer.
16 . The integrated circuit chip of claim 15 , wherein said electroplated metal layer comprises electroplated gold.
17 . The integrated circuit chip of claim 15 , wherein said electroplated metal layer comprises electroplated copper.
18 . The integrated circuit chip of claim 15 , wherein said insulating layer comprises a polymer.
19 . The integrated circuit chip of claim 15 , wherein said insulating layer comprises polyimide.
20 . The integrated circuit chip of claim 15 , wherein said insulating layer comprises benzocyclobutene (BCB).