Time-domain equalization for discrete multi-tone systems
View Patent ↗A multiple carrier communication system includes a primary impulse shortening filter that receives an output signal of an analog to digital converter and accepts coefficients. A secondary impulse shortening filter receives the output signal of the analog to digital converter, outputs an output signal, and passes coefficients to the primary impulse shortening filter. A reference signal generator outputs a reference signal. A comparator compares the output signal and the reference signal and outputs a resulting error signal. An adaptive processor computes coefficients for the secondary impulse shortening filter based on the error signal.
1. A method for transmitting information in a VDSL communication system comprising:
selecting a cyclic prefix length from a plurality of candidate lengths based on respective bit rates obtained for the candidate lengths; and
adding an end-portion of a block of information bits at a beginning of the block, wherein the added end-block portion has a length equal to the selected cyclic prefix length.
2. The method of claim 1 including transmitting the block of information bits with the end-portion added thereto through a VDSL communication channel.
3. The method of claim 1 wherein selecting a cyclic prefix length includes:
computing a respective maximum bit rate value for each of the candidate lengths; and
identifying a particular one of the candidate lengths having the largest maximum bit rate value of the computed maximum bit rate values.
4. The method of claim 1 including:
transmitting the computed respective bit rates; and
transmitting the block of information bits with the end-portion added thereto.
5. The method of claim 1 wherein selecting comprises determining the signal to noise ratio associated with each of the plurality of candidate lengths.
6. The method of claim 3 comprising:
transmitting the largest maximum bit rate value.
7. A method of dynamically selecting a cyclic prefix length in a VDSL communication system, the method comprising:
computing a respective maximum bit rate value for each of a plurality of candidate cyclic prefix lengths;
identifying a particular one of the candidate cyclic prefix lengths having the largest maximum bit rate value of the computed maximum bit rate values; and
adding an end-portion of a block of information bits at a beginning of the block, wherein the added end-block portion has a length equal to the particular one candidate cyclic prefix length.
8. The method of claim 7 , wherein the candidate cyclic prefix lengths include at least a first length and a second length, the method including:
transmitting data having a cyclic prefix of the first length;
computing a first maximum bit rate value for the cyclic prefix of the first length;
transmitting data having a cyclic prefix of the second length; and
computing a second maximum bit rate value for the cyclic prefix of the second length.
9. The method of claim 7 wherein computing a respective maximum bit rate value comprises determining the signal to noise ratio associated with each of the plurality of candidate cyclic prefix lengths.
10. The method of claim 7 comprising:
transmitting the largest maximum bit rate value.
11. The method of claim 7 wherein:
the computing a respective maximum bit rate value is performed by a discrete multi-tone receiver; and
the identifying a particular one of the candidate cyclic prefix lengths is performed by a discrete multi-tone transmitter.
12. A VDSL communication system comprising:
a VDSL receiver comprising:
logic that computes a bit rate value for each of a plurality of candidate cyclic prefix lengths;
a transmitter that transmits the bit rate values;
a VDSL transmitter comprising:
a receiver that receives the bit rate values;
logic that identifies a particular one of the candidate cyclic prefix lengths having the largest bit rate value of the computed bit rate values.
13. The system of claim 12 wherein the VDSL transmitter comprises:
logic that adds an end-portion of a block of information bits at a beginning of the block, wherein the added end-block portion has a length equal to the particular one candidate cyclic prefix length.
14. The system of claim 12 wherein the logic that computes a bit rate value determines the signal to noise ratio associated with each of the plurality of candidate cyclic prefix lengths.