Method of fabricating organic light emitting diode display device

1. A method of reducing a roughness of a planarization layer covering a thin film transistor in an organic light emitting diode display device, comprising:

annealing and curing the planarization layer after forming a first extension of a via hole in the planarization layer;

providing an ashing treatment to the planarization layer after forming a second extension of the via hole by dry etching; and

providing a surface treatment to the planarization layer after the ashing treatment

wherein the surface treatment comprises at least one of: exposing the planarization layer to a development solution; exposing the planarization layer to extreme ultraviolet rays (EUV); or exposing the planarization layer to ozone (O 3 ) water.

2. The method according to claim 1 , wherein the annealing and curing is performed at a temperature of 200 to 300° C. for 1 to 2 hours.

3. The method according to claim 1 , wherein the ashing treatment is performed at a process pressure of 100-200 mTorr, a source power of 1 kW-2 kW, a bias power of 200-500 W, and an oxygen flow rate of 200-1000 sccm.

4. The method of claim 1 , wherein the planarization layer is a photosensitive material selected from the group consisting of acryl resin, benzocyclobutene (BCB), and polyimide resin.

5. The method of claim 1 , wherein a development solution of the surface treatment comprises tetra methyl ammonium hydroxide.

6. A method of fabricating an organic light emitting diode display device, comprising:

forming a thin film transistor on a substrate;

forming a gate insulating layer on the substrate;

forming an interlayer insulating layer on the substrate;

forming a passivation layer on the entire surface of the substrate;

forming a planarization layer on the passivation layer;

exposing and developing the planarization layer to form a first extension of a via-hole exposing a portion of the passivation layer formed on a source electrode or a portion of the passivation layer formed on a drain electrode of the thin film transistor;

annealing and curing the planarization layer after the exposing and the developing of the planarization layer;

dry etching the passivation layer to form a second extension of the via-hole;

providing an ashing treatment of the planarization layer;

providing a surface treatment after the ashing treatment of the planarization layer;

forming a pixel electrode on the planarization layer connected to the source electrode or the drain electrode through the via-hole;

forming an organic layer including an organic emission layer on the pixel electrode; and

forming an opposite electrode on the entire surface of the substrate,

wherein the surface treatment comprises at least one of: exposing the planarization layer to a development solution; exposing the planarization layer to extreme ultraviolet rays (EUV); or exposing the planaraization layer to ozone (O 3 ) water.

7. The method according to claim 6 , wherein the annealing and curing is performed at a temperature of 200 to 300° C. for 1 to 2 hours.

8. The method according to claim 6 , wherein the annealing and curing is performed at a temperature of 250° C. for 1 hour.

9. The method according to claim 6 , wherein the ashing treatment is performed at a process pressure of 100-200 mTorr, a source power of 1 kW-2 kW, a bias power of 200-500 W, and an oxygen flow rate of 200-1000 sccm.

10. The method according to claim 6 , wherein the ashing treatment is performed at a process pressure of 150 mTorr, a source power of 1.5 kW, a bias power of 350 W, and an oxygen flow rate of 500 sccm.

11. The method of claim 6 , wherein the surface treatment is carried out for 0.5 to 5 minutes.

12. The method of claim 6 , wherein the development solution comprises tetra methyl ammonium hydroxide.

13. The method according to claim 6 , wherein the surface treatment is provided by exposing the planarization layer to a development solution of 2.38 wt % tetra methyl ammonium hydroxide for 1 minute.

14. The method according to claim 6 , wherein the surface treatment is provided by exposing the planarization layer to extreme ultraviolet rays (EUV) and a development solution of 2.38 wt % tetra methyl ammonium hydroxide for 1 minute.

15. The method according to claim 6 , wherein the surface treatment is provided by exposing the planarization layer to continuously ozone water and a development solution of 2.38 wt % tetra methyl ammonium hydroxide for one minute.

16. The method according to claim 6 , wherein the pixel electrode further comprises a reflective layer.

17. The method according to claim 6 , wherein the second extension of the via-hole is formed through dry etching using the planarization layer as a mask.

18. The method according to claim 6 , wherein the dry etching is carried out by reactive ion etching, plasma etching, or inductively coupled plasma etching.

19. The method of claim 6 , wherein the planarization layer is a photosensitive material selected from the group consisting of acryl resin, benzocyclobutene (BCB), and polyimide resin.