IP Library Granted Patent US 8,148,785
Granted Patent B2
US 8,148,785 · App. 12/210,775 · Granted Apr 3, 2012

Semiconductor device

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,148,785
App. No.
12/210,775
Granted
Apr 3, 2012
Kind
B2
Abstract

A semiconductor device can output a reference voltage for an arbitrary potential and can detect the voltage of each cell in a battery including multiple cells very precisely. The device includes a depletion-type MOSFET 21 and an enhancement type MOSFET 22 , and has a floating structure that isolates depletion-type MOSFET 21 and enhancement type MOSFET 22 from a ground terminal. The depletion-type MOSFET 21 and enhancement type MOSFET 22 are connected in series to each other, wherein the depletion-type MOSFET 21 is connected to high-potential-side terminal and the enhancement type MOSFET 22 is connected to low-potential-side terminal. The semiconductor device having the configuration described above is disposed in a voltage detecting circuit section in a control IC for a battery including multiple cells.

Claims (24)

1. A semiconductor device comprising:

a substrate of a first conductivity type;

a first well layer of a second conductivity type disposed in a surface portion of the substrate;

a second well layer of the first conductivity type disposed in a surface portion of the first well layer;

a third well layer of the first conductivity type disposed in the surface portion of the first well layer, the third well layer being spaced apart from the second well layer;

a depletion-type MOSFET disposed in the second well layer; and

an enhancement-type MOSFET disposed in the third well layer;

wherein the depletion-type MOSFET comprises:

a first drain layer of the second conductivity type disposed in a surface portion of the second well layer;

a first source layer of the second conductivity type disposed in the surface portion of the second well layer, the first source layer being spaced apart from the first drain layer;

a depletion layer of the second conductivity type disposed in the surface portion of the second well layer, the depletion layer being in contact with the first drain layer and the first source layer;

a first pickup layer of the first conductivity type disposed in the surface portion of the second well layer; and

a first gate electrode above the depletion layer with a first gate oxide film interposed between the depletion layer and the first gate electrode; and

wherein the enhancement-type MOSFET comprises:

a second drain layer of the second conductivity type disposed in a surface portion of the third well layer;

a second source layer of the second conductivity type disposed in the surface portion of the third well layer, the second source layer being spaced apart from the second drain layer;

a channel layer of the first conductivity type disposed in the surface portion of the third well layer, the channel layer being in contact with the second drain layer and the second source layer;

a second pickup layer of the first conductivity type disposed in the surface portion of the third well layer; and

a second gate electrode above the channel layer with a second gate oxide film interposed between the channel layer and the second gate electrode;

the semiconductor device further comprising:

an output terminal connected electrically to the first gate electrode, the first source layer, the second gate electrode and the second drain layer;

a high-potential-side terminal connected electrically to the first drain layer; and

a low-potential-side terminal connected electrically to the first pickup layer, the second source layer and the second pickup layer.

2. The semiconductor device according to claim 1 , wherein the semiconductor device feeds a reference voltage to a reference-potential-side of a comparator that compares a voltage of each cell in a battery comprising a plurality of the cell with the reference voltage.

Assignments (3)
MERGER AND CHANGE OF NAME Recorded Aug 26, 2011
From: FUJI ELECTRIC SYSTEMS CO., LTD. (FES); FUJI TECHNOSURVEY CO., LTD. (MERGER BY ABSORPTION)
To: FUJI ELECTRIC CO., LTD.
Reel/Frame 026970/0872 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 20, 2010
From: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.
To: FUJI ELECTRIC SYSTEMS CO., LTD.
Reel/Frame 024252/0438 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 6, 2008
From: YAMAJI, MASAHARU; KITAMURA, AKIO
To: FUJI ELECTRIC DEVICE TECHNOLOGY., LTD.
Reel/Frame 021795/0755 →