IP Library Granted Patent US 7,911,366
Granted Patent B2
US 7,911,366 · App. 12/212,039 · Granted Mar 22, 2011

Gray code current mode analog-to-digital converter

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Quick Facts
Patent No.
US 7,911,366
App. No.
12/212,039
Granted
Mar 22, 2011
Kind
B2
Abstract

One embodiment of the present invention is a Gray code current-mode analog to digital (ADC) converter using a Gray code current-mode ADC building block. The Gray code current-mode ADC building block can produce a Gray code bit and a current output that is sent to a next Gray code ADC building block. In one embodiment, the Gray code current-mode ADC building block does not use a voltage comparator in a signal path of the current output. In one embodiment, an 8 bit analog-to-digital converter can have a 65 ns conversion time and consume only 10 mW of power with a single +5.0V supply.

Claims (34)

1. A Gray code current-mode analog to digital (ADC) converter using a Gray code current-mode ADC building block, the Gray code current-mode ADC building block being used to produce a Gray code bit and a current output that is sent to a next Gray code ADC building block, wherein the Gray code current-mode ADC building block does not use a voltage comparator in a signal path of the current output;

wherein a pair of transistors are used to cause a current in a first path if I sig >I REF and down a second path if I sig <I REF ; and

wherein Op amps are used to provide feedback to the pair of transistors.

2. The Gray code current-mode ADC converter of claim 1 ;

wherein the Gray code current-mode ADC building block includes an output current mirror.

3. The Gray code current-mode ADC converter of claim 2 ;

wherein the output current mirror doubles a current input into the output current mirror.

4. The Gray code current-mode ADC converter of claim 3 , further comprising a polarity inverting current mirror to invert the polarity of one possible input to the output current mirror.

5. The Gray code current-mode ADC converter of claim 1 ;

wherein the current output is not clocked before flowing to the next Gray code current-mode ADC building block.

6. The Gray code current-mode ADC converter of claim 1 ;

wherein two Gray code current-mode ADC building blocks are used to produce a single Gray code bit.

7. The Gray code current-mode ADC converter of claim 1 , wherein one of the Op amps is referenced to a first voltage and another of the Op amps is referenced to a second voltage less than the first voltage to prevent contention between the Op amps.

8. The Gray code current-mode ADC converter of claim 7 , wherein the pair of transistors are connected at a node and the voltage excursion at the node is limited to the first voltage minus the second voltage.

9. The Gray code current-mode ADC converter of claim 8 , wherein the first voltage minus the second voltage is about 100 mV.

10. The Gray code current-mode ADC converter of claim 1 , wherein the pair of transistors are connected at a node; and wherein the Op amps reduce the input impedance at the node.

11. A Gray code current-mode ADC building block for a Gray code current-mode Analog to Digital (ADC) converter comprising:

a pair of transistors operably connected to a current input, I sig , and reference current, I REF , wherein a current output of the pair of transistors is formed in a first path if I sig >I REF and in a second path if I sig <I REF ;

an output current mirror that doubles an input current to the current mirror to produce a current output of the Gray code current-mode ADC building block that is sent to the next Gray code current-mode ADC building block; wherein the Gray code current mode ADC building block also produces a Gray code bit; and

wherein Op amps are used to provide feedback to the pair of transistors.

12. The Gray code current-mode ADC building block of claim 11 ;

wherein the current output is not clocked before flowing to the next Gray code ADC building block.

13. The Gray code current-mode ADC building block of claim 11 , further comprising a polarity inverting current mirror to invert the polarity of one possible input to the output current mirror.

14. The Gray code current-mode ADC building block of claim 11 ;

wherein two Gray code current-mode ADC building blocks are used to produce a single Gray code bit.

15. The Gray code current-mode ADC building block of claim 11 ;

wherein the first path goes to the output current mirror; and

wherein a second path goes to a second output current mirror.

16. The Gray code current-mode ADC building block of claim 15 ;

wherein a pair of the Gray code current-mode ADC building blocks are used to produce a Gray code bit.

17. The Gray code current-mode ADC building block of claim 11 , wherein one of the Op amps is referenced to a first voltage and another of the Op amps is referenced to a second voltage less than the first voltage to prevent contention between the Op amps.

18. The Gray code current-mode ADC building block of claim 17 , wherein the pair of transistors are connected at a node and the voltage excursion at the node is limited to the first voltage minus the second voltage.

19. The Gray code current-mode ADC building block of claim 18 , wherein the first voltage minus the second voltage is about 100 mV.

20. The Gray code current-mode ADC building block of claim 11 , wherein the pair of transistors are connected at a node; and wherein the Op amps reduce the input impedance at the node.

Assignments (8)
SECURITY AGREEMENT Recorded Jul 9, 2021
From: MAXLINEAR, INC.; MAXLINEAR COMMUNICATIONS, LLC; EXAR CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 056816/0089 →
RELEASE OF SECURITY INTEREST Recorded Jun 23, 2021
From: MUFG UNION BANK, N.A.
To: MAXLINEAR, INC.; EXAR CORPORATION; MAXLINEAR COMMUNICATIONS LLC
Reel/Frame 056656/0204 →
SUCCESSION OF AGENCY (REEL 042453 / FRAME 0001) Recorded Jul 1, 2020
From: JPMORGAN CHASE BANK, N.A.
To: MUFG UNION BANK, N.A.
Reel/Frame 053115/0842 →
MERGER AND CHANGE OF NAME Recorded Oct 4, 2017
From: EAGLE ACQUISITION CORPORATION; EXAR CORPORATION; EXAR CORPORATION
To: EXAR CORPORATION
Reel/Frame 044126/0634 →
SECURITY AGREEMENT Recorded May 12, 2017
From: MAXLINEAR, INC.; ENTROPIC COMMUNICATIONS, LLC (F/K/A ENTROPIC COMMUNICATIONS, INC.); EXAR CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 042453/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2015
From: STIFEL FINANCIAL CORP.
To: EXAR CORPORATION; CADEKA MICROCIRCUITS, LLC
Reel/Frame 035168/0384 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 12, 2014
From: HU, ZONGGI
To: EXAR CORPORATION
Reel/Frame 033092/0951 →
SECURITY INTEREST Recorded May 29, 2014
From: EXAR CORPORATION; CADEKA MICROCIRCUITS, LLC
To: STIFEL FINANCIAL CORP.
Reel/Frame 033062/0123 →