Semiconductor device with a logic circuit
View Patent ↗The logic gate of the present invention is of a configuration that includes a first transistor, a second transistor, and a connection-switching unit. The first transistor receives a first voltage at its source, a first input signal at its gate, and supplies a first output signal from its drain. The second transistor receives a second voltage that is lower than the first voltage at its source, receives a second input signal at its gate, and supplies a second output signal from its drain. The connection-switching unit is connected between the drains of the first transistor and the second transistor for connecting and cutting off the first transistor and the second transistor.
1. A semiconductor device with a logic circuit, the logic circuit comprising first and second power supply lines supplied respectively with first and second power supply voltages, first and second input nodes supplied respectively with first and second input signals, first and second output nodes, first and second control nodes supplied respectively with first and second control signals, the first control signal being opposite in phase to the second control signal, a first transistor circuit having a first transistor of a first channel type and coupled to the first power supply line, the first input node and the first output node, a second transistor circuit having a second transistor of a second channel type and coupled to the second power supply line, the second input node and the second output node, a third transistor of the second channel type coupled between the first and second output nodes and having a gate connected to the first control node, and a fourth transistor of the first channel type connected between the first and second output nodes and having a gate connected to the second control node, each of the third and fourth transistors being larger in threshold voltage in absolute value than each of the first and second transistors.
2. The device as claimed in claim 1 , wherein the first and second input nodes are connected in common to make the first input signal identical with the second input signal.
3. The device as claimed in claim 1 , further comprising a fifth transistor of the second channel type connected in series with the third transistor between the first and second output nodes and having a gate connected to the first input node, and a sixth transistor of the first channel type connected in series with the fourth transistor between the first and second output nodes and having a gate connected to the second input node.
4. The device as claimed in claim 1 , wherein the logic circuit further comprises a first clamp transistor of the first channel type coupled between the first power supply line and the first output node and having a gate connected to the second control node and a second clamp circuit of the second channel type coupled between the second power supply line and the second output node and having a gate connected to the first control node.
5. The device as claimed in claim 2 , wherein the logic circuit further comprises a first clamp transistor of the first channel type coupled between the first power supply line and the first output node and having a gate connected to the second control node and a second clamp circuit of the second channel type coupled between the second power supply line and the second output node and having a gate connected to the first control node.
6. The device as claimed in claim 3 , wherein the logic circuit further comprises a first clamp transistor of the first channel type coupled between the first power supply line and the first output node and having a gate connected to the second control node and a second clamp circuit of the second channel type coupled between the second power supply line and the second output node and having a gate connected to the first control node.
7. A semiconductor device with a logic circuit, the logic circuit comprising first and second power supply lines respectively supplied with first and second power supply voltages, first and second input nodes supplied respectively with first and second input signals, first and second output nodes, a first transistor of a first channel type coupled between the first power supply line and the first output node and having a gate connected to the first input node, a second transistor of a second channel type coupled between the second power supply line and the second output node and a gate connected to the second input node, a third transistor of the first channel type coupled between the first and second output nodes and having a gate connected to the second input node, and a fourth transistor of the second channel type coupled between the first and second output nodes and having a gate connected to the first input node, each of the third and fourth transistors being larger in threshold voltage in absolute value than each of the first and second transistors.
8. The device as claimed in claim 7 , wherein the logic gate further comprises third and fourth input nodes, a fifth transistor of the first channel type coupled in parallel to the first transistor between the first power supply line and the first output node and having a gate connected to the third input node, a sixth transistor of the second channel type coupled in series with the second transistor between the second power supply line and the second output node and having a gate connected to the fourth input node, a seventh transistor of the first channel type coupled in parallel to the third transistor between the first and second output nodes and having a gate connected to the fourth input node, and an eighth transistor of the second channel type coupled in series with the fourth transistor between the first and second output nodes and having a gate connected to the third input node, each of the seventh and eighth transistors being larger in threshold voltage in absolute value than each of the first, second, fifth and sixth transistors.
9. The device as claimed in claim 7 , wherein the logic gate further comprises third and fourth input nodes, a fifth transistor of the first channel type coupled in series with the first transistor between the first power supply line and the first output node and having a gate connected to the third input node, a sixth transistor of the second channel type coupled in parallel to the second transistor between the second power supply line and the second output node and having a gate connected to the fourth input node, a seventh transistor of the first channel type coupled in series with third transistor between the first and second output nodes and having a gate connected to the fourth input node, and an eighth transistor of the second channel type coupled in parallel to the fourth transistor between the first and second output nodes and having a gate connected to the third input node, each of the seventh and eighth transistors being larger in threshold voltage in absolute value than each of the first, second, fifth and sixth transistors.
10. The device as claimed in claim 8 , wherein the logic circuit further comprises a ninth transistor of the second channel type coupled in parallel to the eighth transistor and having a gate supplied with a control signal.
11. The device as claimed in claim 9 , wherein the logic circuit further comprises a ninth transistor of the first channel type coupled in parallel to the fifth transistor and having a gate supplied with a control signal.