Display apparatus, driving method for display apparatus and electronic apparatus

1. A display apparatus comprising:

a plurality of pixel circuits arrayed in a matrix, each of the pixel circuits including a switching transistor and a liquid crystal cell; and

at least one waveform shaping circuit connected to a gate electrode of the switching transistor,

the waveform shaping circuit including:

a gate electrode of a first buffer PMOS transistor directly electrically connected to a gate electrode of a first buffer NMOS transistor;

a gate electrode of a second buffer PMOS transistor directly electrically connected to a gate electrode of a second buffer NMOS transistor;

a source of the first buffer NMOS transistor directly electrically connected to a drain of a third buffer NMOS transistor;

a source of the second first buffer PMOS transistor directly electrically connected to a source of a third buffer PMOS transistor;

a source electrode of the third buffer NMOS transistor directly electrically connected to a source electrode of the second buffer NMOS transistor;

a drain of the first buffer PMOS transistor directly electrically connected to a drain of the first buffer NMOS transistor and to said gate electrode of the second buffer PMOS transistor;

a drain of the second buffer PMOS transistor directly electrically connected to a drain of the second buffer NMOS transistor;

a drain of the third buffer PMOS transistor directly electrically connected to said drain of the first buffer PMOS transistor; and

a gate electrode of the third buffer PMOS transistor directly electrically connected to a gate electrode of the third buffer NMOS transistor,

wherein the waveform shaping circuit is a NAND circuit of a CMOS configuration that indicates an inverted logic output with respect to an input thereto,

wherein the NAND circuit of the CMOS configuration starts an operation at a rising edge or a falling edge of an enable signal when the enable signal is inputted to the NAND circuit of the CMOS configuration, and

wherein the rising edge of the enable signal occurs simultaneously with each rising edge of a gate pulse supplied to the plurality of pixels arrayed in the matrix.

2. The display apparatus according to claim 1 , further comprising:

a gate electrode of a switching device directly electrically connected to said gate electrode of the first buffer PMOS transistor and to said gate electrode of the first buffer NMOS transistor.

3. The display apparatus according to claim 2 , further comprising:

a drain electrode of the switching device directly electrically connected to an electrode of a storage capacitance and to an electrode of an electro-optical element.

4. The display apparatus according to claim 2 , further comprising:

a gate electrode of a different switching device directly electrically connected to said drain of the second buffer PMOS transistor and to said drain of the second buffer NMOS transistor.

5. The display apparatus according to claim 2 , further comprising:

a power supply voltage supply line directly electrically connected to said source of the second buffer PMOS transistor and to said source of the third buffer PMOS transistor.

6. The display apparatus according to claim 5 , wherein said power supply voltage supply line is configured to receive a power supply voltage.

7. The display apparatus according to claim 6 , further comprising:

a different power supply voltage supply line directly electrically connected to said source of the third buffer NMOS transistor and to said source of the second buffer NMOS transistor.

8. The display apparatus according to claim 7 , wherein said different power supply voltage supply line is configured to receive a different power supply voltage, said different power supply voltage differing from said power supply voltage.

9. The display apparatus according to claim 8 , further comprising:

a common voltage wiring line directly electrically connected to another electrode of the storage capacitance and to an opposing electrode of the electro-optical element.

10. The display apparatus according to claim 8 , wherein said common voltage wiring line is configured to receive a common voltage, said common voltage differing from said power supply voltage and said different power supply voltage.

11. The display apparatus according to claim 1 , further comprising:

an electrode of a gate line capacitance directly electrically connected to said drain of the second buffer PMOS transistor and to said drain of the second buffer NMOS transistor.

12. The display apparatus according to claim 1 , further comprising:

a substrate having a light blocking region, said first buffer NMOS transistor and said second buffer NMOS transistor being in said light blocking region.

13. An electronic apparatus comprising the display apparatus according to claim 1 .