IP Library Granted Patent US 7,642,103
Granted Patent B2
US 7,642,103 · App. 12/213,908 · Granted Jan 5, 2010

Method of fabricating semiconductor device

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Quick Facts
Patent No.
US 7,642,103
App. No.
12/213,908
Granted
Jan 5, 2010
Kind
B2
Abstract

Dicing lines extending longitudinally and transversely, and chip areas surrounded by the dicing lines are formed in a resist mask. Critical-dimension patterns are formed in the dicing lines so as to be paired while placing the center line thereof in between. The dimensional measurement of the resist film having these patterns formed therein is made under a CD-SEM, by specifying a measurement-target chip area out of a plurality of chip areas, and by specifying a position of a critical-dimension pattern on the left thereof. Then, the distance of two linear portions configuring the critical-dimension pattern is measured, wherein a portion at a point of measurement on the measurement-target chip area side as viewed from the center line of the dicing line is measured.

Claims (14)

1. A method of fabricating a semiconductor device comprising the steps of:

transferring a circuit pattern within chip areas, and transferring a critical-dimension pattern within a dicing line; and

measuring a dimension of a critical-dimension pattern transferred by the same shot of light exposure with a measurement-target chip area, as the critical-dimension pattern, one being transferred having, as viewed from the center line of the dicing line, a portion on the same side with a chip area transferred by the same shot of light exposure, separated from another portion which resides on the opposite side.

2. The method of fabricating a semiconductor device according to claim 1 , wherein the critical-dimension patterns are measured under a critical-dimension scanning electron microscope.

3. The method of fabricating a semiconductor device according to claim 1 , wherein as the critical-dimension pattern, one is transferred having at least two linear portions arranged so as to be spaced from each other.

4. The method of fabricating a semiconductor device according to claim 1 , wherein the critical-dimension patterns are transferred in at least two points by a single shot of light exposure within the dicing line.

5. The method of fabricating a semiconductor device according to claim 4 , wherein the critical-dimension patterns are formed in two points placing the circuit area in between.

6. The method of fabricating a semiconductor device according to claim 1 , wherein said step of measuring the critical-dimension pattern comprises the steps of:

specifying a position of the critical-dimension pattern on the basis of the center line of the dicing line; and

measuring a portion of the critical-dimension pattern, as viewed from the center line of the dicing line, on the same side with the chip area.

7. The method of fabricating a semiconductor device according to claim 1 , wherein, as the critical-dimension pattern, one is transferred having:

a first linear portion formed, as viewed from the center line of the dicing line, on the same side with the chip areas transferred by the same shot of light exposure, and extending in parallel with the center line; and

a second linear portion spaced from the first linear portion, and extending in the direction normal to said center line.

8. The method of fabricating a semiconductor device according to claim 1 , further comprising a step of displaying results of the measurement on a display, together with a measurement-target chip area.

Assignments (3)
CHANGE OF ADDRESS Recorded Dec 23, 2016
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 041188/0401 →
CHANGE OF NAME Recorded Jul 9, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024651/0744 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 4, 2010
From: FUJITSU LIMITED
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 024023/0243 →