Semiconductor device having plural DRAM memory cells and a logic circuit and method for manufacturing the same
View Patent ↗A memory cell capacitor (C 3 ) of a DRAM is formed by use of a MIM capacitor which uses as its electrode a metal wiring line of the same layer (M 3 ) as metal wiring lines within a logic circuit (LOGIC), thereby enabling reduction of process costs. Higher integration is achievable by forming the capacitor using a high dielectric constant material and disposing it above a wiring layer in which bit lines (BL) are formed. In addition, using 2T cells makes it possible to provide a sufficient signal amount even when letting them operate with a low voltage. By commonizing the processes for fabricating capacitors in analog (ANALOG) and memory (MEM), it is possible to realize a semiconductor integrated circuit with the logic, analog and memory mounted together on one chip at low costs.
1. A semiconductor integrated circuit device comprising:
a semiconductor substrate having a main surface;
a memory cell of a random access memory (DRAM) arranged at a first region on the main surface and including a first MISFET and a first capacitor element such that the first capacitor element is electrically connected to a source-drain path of the first MISFET,
wherein the first MISFET includes a source region and a drain region each formed in the semiconductor substrate, a gate electrode, a gate insulating film formed on the semiconductor substrate and silicide layers formed on the source region, the drain region and the gate electrode;
a logic circuit arranged at a second region of the main surface including a second MISFET,
wherein the second MISFET includes a source region and a drain region each formed in the semiconductor substrate, a gate electrode, a gate insulating film formed on the semiconductor substrate and silicide layers formed on the source region, the drain region and the gate electrode;
a first insulating film formed over the first MISFET and the second MISFET,
a lower electrode of the first capacitor element formed on the first insulating,
a dielectric insulating film of the first capacitor element formed on the lower electrode of the first capacitor element,
a higher electrode of the first capacitor element formed on the dielectric insulating file of the first capacitor element;
a second insulating film formed over the first capacitor element and the first insulating film; and
a second capacitor element formed over the second insulating film,
a lower electrode of the second capacitor element formed on the same level layer a wiring layer,
a dielectric insulating film of the second capacitor element formed on the lower electrode of the second capacitor element,
a higher electrode of the second capacitor element formed on the dielectric insulating film of the second capacitor element, and
a third insulating film formed over the second capacitor element and the second insulating film,
wherein the third insulating film having a via hole for connecting the wiring layer.
2. A semiconductor integrated circuit device according to claim 1 , wherein a thickness of the dielectric insulating film of the second capacitor element is greater than a thickness of the dielectric insulating film of a third capacitor element.
3. A semiconductor integrated circuit device according to claim 1 , wherein the wiring layer is comprised of a copper wiring layer.
4. A semiconductor integrated circuit device according to claim 1 , wherein the second capacitor element is comprised of a MIS capacitor.
5. A semiconductor integrated circuit device according to claim 1 , wherein the first capacitor element is comprised of a MIS capacitor.
6. A semiconductor integrated circuit device according to claim 1 , wherein the logic circuit constitutes a processor.
7. A semiconductor integrated circuit device according to claim 1 , wherein an analog circuit includes the second capacitor element.