IP Library Granted Patent US 8,180,978
Granted Patent B1
US 8,180,978 · App. 12/214,206 · Granted May 15, 2012

Address locked loop

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Quick Facts
Patent No.
US 8,180,978
App. No.
12/214,206
Granted
May 15, 2012
Kind
B1
Abstract

An address locked loop (ALL) apparatus for address recycling is provided. The apparatus comprises a block of memory further comprising a plurality of buffers configured to store a plurality of incoming packets, an address stack configured for storing of a plurality of free addresses, an address locked loop (ALL) control block configured to provide an arbitrated interface with the address stack for filling address requests by a local process and for returning free addresses from the local process to the address stack, and a stack address counter configured to maintain count of the available free addresses remaining on the address stack.

Claims (8)

1. An address locked loop (ALL) apparatus for address recycling comprising:

a block of memory comprising a plurality of buffers; each said buffer has the same byte size; said block of memory is configured to store a plurality of incoming packets; wherein said incoming packet is stored in at least one said buffer if a byte size of said incoming packet is less than said byte size of said buffer; and wherein said incoming packet is stored in a plurality of buffers if said byte size of said incoming packet is greater than said byte size of one said buffer;

an address stack configured for storing of a plurality of free addresses; wherein each said free address corresponds to one said free buffer;

an address locked loop (ALL) control block coupled to said address stack; said address locked loop control block configured to provide an arbitrated interface with said address stack for filling address requests by a local process and for returning free addresses from said local process to said address stack; wherein said address locked loop (ALL) control block further comprises:

an address locked loop (ALL) control feedback interface configured to send a feedback signal to a previous local process; and configured to receive a feedback signal from a following local process; wherein said ALL control feedback interface is configured to provide a data flow control between said previous local process and said following local process; and wherein said ALL control feedback interface further comprises:

a plurality of flags; a first said flag is configured to indicate said local process status; a second said flag is configured to indicate said previous process status; a third said flag is configured to indicate said following process status;

and

a stack address counter coupled to said ALL; said stack address counter configured to maintain count of said available free addresses remaining on said address stack.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 23, 2018
From: REMEC BROADBAND WIRELESS HOLDINGS, INC.
To: RBW ACQUISITION CO., LLC
Reel/Frame 045335/0849 →
CHANGE OF NAME Recorded Mar 23, 2018
From: RBW ACQUISITION CO., LLC
To: REMEC BROADBAND WIRELESS NETWORKS, LLC
Reel/Frame 045692/0293 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 5, 2012
From: WIDEBAND SEMICONDUCTOR, INC.
To: REMEC BROADBAND WIRELESS HOLDINGS, INC.
Reel/Frame 029408/0085 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 12, 2008
From: FAGERLUND, RICHARD J.; ISAKSEN, DAVID B.; SANFILIPPO, PHILIP R.; TANKHILEVICH, BORIS G.
To: WIDEBAND SEMICONDUCTORS, INC.
Reel/Frame 021545/0926 →