Thin film transistor (TFT) and flat panel display including the TFT and their methods of manufacture
View Patent ↗A Thin Film Transistor (TFT) reduces interconnection resistance of source/drain electrodes, prevents contamination from an active layer, reduces contact resistance between a pixel electrode and the source/drain electrodes, smoothly supplies hydrogen to the active layer and has high mobility, on-current characteristics, and threshold voltage characteristics The TFT includes an active layer having a channel region and source/drain regions, a gate electrode supplying a signal to the channel region, source/drain electrodes respectively connected to the source/drain regions and including at least one of Ti, a Ti alloy, Ta, and a Ta alloy; and an insulating layer interposed between the source/drain electrodes and the active layer and including silicon nitride.
1. A method of manufacturing a Thin Film Transistor (TFT), the method comprising:
forming an active layer and a gate electrode insulated from each other by a gate insulating layer on a substrate and forming an InterLevel Dielectric (ILD) layer to cover the active layer and the gate electrode, at least one of the gate insulating layer and the ILD layer containing silicon nitride;
thermally treating the ILD layer;
forming source/drain contact holes in at least one of the gate insulating layer and the ILD layer; and
forming source/drain electrodes, the source/drain electrodes being arranged on the ILD layer, contacting the active layer through the source/drain contact holes,
wherein forming the source/drain electrodes comprises:
forming a first metallic layer pattern arranged on the ILD layer and contacting the active layer through the source/drain contact holes, said first metallic layer formed of Cr, Cr alloy, Mo, or Mo alloy;
forming a second metallic layer pattern on said first metallic layer and formed of Al, AlSi, AlNd, or AlCu; and
forming a third metallic layer pattern on said second metallic layer and formed of Ti, Ti alloy, Ta, or Ta alloy,
wherein the active layer comprises a poly silicon,
wherein the thermally treating of the ILD laver must be performed prior to forming the source and drain electrodes.
2. The method of claim 1 , further comprising forming a protective layer pattern on a first metallic layer pattern before forming the second metallic layer pattern.
3. A method of manufacturing a flat panel display, the method comprising: manufacturing a Thin Film Transistor (TFT) including:
forming an active layer and a gate electrode insulated from each other by a gate insulating layer on a substrate and forming an InterLevel Dielectric (ILD) layer to cover the active layer and the gate electrode, at least one of the gate insulating layer and the ILD layer containing silicon nitride;
thermally treating the ILD layer;
forming source/drain contact holes in at least one of the gate insulating layer and the ILD layer; and
forming source/drain electrodes, the source/drain electrodes being arranged on the ILD layer, contacting the active layer through the source/drain contact holes,
forming an insulating layer to cover the TFT; and
forming a pixel electrode connected to the source/drain electrodes of the TFT on the insulating layer,
wherein forming the source/drain electrodes comprises:
forming a first metallic layer pattern arranged on the ILD layer and contacting the active layer through the source/drain contact holes, said first metallic layer formed of Cr, Cr alloy, Mo, or Mo alloy;
forming a second metallic layer pattern on said first metallic layer and formed of Al, AlSi, AlNd, or AlCu; and
forming a third metallic layer pattern on said second metallic layer and formed of Ti, Ti alloy, Ta, or Ta alloy,
wherein the active layer comprises a poly silicon,
wherein the thermally treating of the ILD laver must be performed prior to forming the source and drain electrodes.