Nonvolatile semiconductor memory device
View Patent ↗A sub-decoder element provided corresponding to each word line is constructed by the same conductive type MOS transistors. The sub-decoder elements are arranged in a plurality of columns such that the layout of active regions for forming the sub-decoder elements is inverted in a Y direction and displaced by one sub-decoder element in an X direction. The arrangement of the sub-decoder elements is adjusted such that high voltage is not applied to both of gate electrodes adjacent in the Y direction. A well voltage of a well region for forming the sub-decoder element group is set to a voltage level such that a source to substrate of the transistor of the sub-decoder element is set into a deep reversed-bias state. In a nonvolatile semiconductor memory device, the leakage by a parasitic MOS in a sub-decoder circuit or word line driving circuit to which a positive or negative high voltage is supplied, can be suppressed.
1. A nonvolatile semiconductor memory device, comprising:
a memory cell array including a plurality of memory cells arranged in rows and columns;
a plurality of word lines, arranged corresponding to the memory cell rows, each connected to the memory cells on a corresponding row;
subdecode circuitry including subdecode elements arranged corresponding to the respective word lines, for setting voltages of the word lines in accordance with a set of source signals and a set of gate signals;
block decode circuitry for producing the source signals in accordance with an address signal; and
gate decode circuitry for producing the gate signals in accordance with an address signal, and
each subdecode element including first and second transistor of a common conductivity type each having a source and a gate, the gates of the first and second transistors being supplied with first and second gate signals, respectively, from said gate decode circuitry, the sources of said first and second transistors being supplied with first and second source signal, respectively, from the block decode circuitry, and drains of said first and second transistors being coupled commonly to a corresponding word line, and
the subdecode elements being arranged such that contacts to the gates are aligned on a line, contacts to the sources are arranged linearly and adjacent subdecode elements are arranged so as for their second transistors to share a region of the respective sources.
2. The nonvolatile semiconductor memory device according to claim 1 , wherein the subdecode elements are arranged in the subdecode circuitry in alignment on a plurality of lines such that nearest neighboring gates are prevented from being supplied concurrently with a high voltage for programming or erasure.
3. The nonvolatile semiconductor memory device according to claim 1 , wherein the subdecode elements are arranged in the subdecode circuitry such that a nearest neighboring gate with respect to a gate receiving a high voltage for programming or erasure is supplied with a voltage different in polarity from the high voltage.