Level shifter, interface driver circuit and image display system
The present invention relates to a level shifter receiving a control signal to produce a first and a second driving voltage, comprising a first and a second capacitor, and a first and a second self-bias circuit for respectively providing a supply path to couple to a direct current bias voltage source, and charging the first and the second capacitor, wherein the first and the second capacitor can boost the control signal to produce the first and the second driving voltage respectively. The present invention also provides an image display system, comprising an interface driver circuit that uses the first and the second driving voltage produced by the level shifter to generate a high-level voltage output signal.
1 . A level shifter for receiving a control signal to generate a first and a second driving voltage, comprising:
a first and a second capacitor; and
a first and a second self-bias circuit for respectively providing a supply path to couple to a direct current bias voltage source and charging the first and the second capacitor;
wherein the first and the second capacitor can respectively boost the control signal to generate the first and the second driving voltages respectively.
2 . The level shifter according to claim 1 , wherein the first and the second self-bias circuit comprise a PMOS transistor and a diode-connected transistor respectively.
3 . The level shifter according to claim 2 , wherein the PMOS transistor is serially connected to the diode-connected transistor, and receives the direct current bias voltage source to form the supply path.
4 . The level shifter according to claim 2 , wherein the control signal is used to control the ON/OFF of the PMOS transistor to further control the ON/OFF of the supply path.
5 . The level shifter according to claim 1 , wherein the first and the second self-bias circuits are respectively parallel connected to the first and the second capacitor.
6 . The level shifter according to claim 1 , wherein one end of the first and the second capacitor is respectively coupled to the control signal so that the first and the second capacitor can boost the control signal so as to generate the first and second driving voltages respectively.
7 . The level shifter according to claim 6 , wherein the first and the second capacitors are respectively coupled to the supply path at another end and generates the driving voltage at the other end respectively.
8 . An interface driver circuit for receiving a control signal and generating a voltage output signal, comprising:
a driver circuit having a first and a second driver transistor to control the level of the voltage output signal; and
a level shifter for receiving and boosting the control signal to control the gate voltage of the first and the second driver transistors of the driver circuit;
wherein the level shifter comprises:
a first and a second capacitor; and
a first and a second self-bias circuit for respectively providing a direct current bias voltage source to the supply path of the gate of the first and the second driver transistors, and charging the first and the second capacitor respectively;
wherein the first and the second capacitor can respectively boost the control signal to generate the gate voltages of the first and the second driver transistors respectively.
9 . The interface driver circuit according to claim 8 , wherein the first and the second driver transistors are a thin-film transistor.
10 . The interface driver circuit according to claim 8 , wherein the driver circuit further receives a high-level direct current driving voltage source.
11 . The interface driver circuit according to claim 8 , wherein the driver circuit further receives a low-level direct current driving voltage source.
12 . The interface driver circuit according to claim 8 , wherein the first and the second driver transistors have different dimensions.
13 . The interface driver circuit according to claim 8 , wherein the first and the second self-bias circuits further comprise a PMOS transistor and a diode-connected transistor respectively.
14 . The interface driver circuit according to claim 8 , wherein the PMOS is serially connected to the diode-connected transistor and receives the direct current bias voltage source to form the supply path.
15 . The interface driver circuit according to claim 8 , wherein the control signal is used to control the ON/OFF of the PMOS transistor to further control the ON/OFF of the supply path.
16 . An image display system, comprising:
an interface driver circuit for receiving a control signal and generating a voltage output signal;
a driver circuit having a set of serially connected first and second driver transistors to control the level of the voltage output; and
a level shifter for receiving and boosting the control signal to control the gate voltage of the first and second driver transistors of the driver circuit;
wherein the level shifter comprises:
a first and a second capacitors;
a first and a second PMOS transistors for respectively providing a direct current voltage source to the supply path of the gate of the first and second driver transistors, and charging the first and the second capacitor respectively; and
a first and a second diode-connected transistor parallel connected to the first and the second PMOS transistors respectively so as to control the voltage level of the gate of the first and second driver transistors provided by the direct current voltage source;
wherein the first and the second capacitors can respectively boost the control signal to generate the gate voltages of the first and the second driver transistors respectively.
17 . The image display system according to claim 16 , wherein the first and the second driver transistors are respectively a thin-film transistor.
18 . The image display system according to claim 16 , wherein the driver circuit further receives a high-level direct current driving voltage source.
19 . The image display system according to claim 16 , wherein the driver circuit further receives a low-level direct current driving voltage source.
20 . The image display system according to claim 16 , wherein the first and the second driver transistors have different dimensions.
21 . The image display system according to claim 16 , wherein the first and the second diode-connected transistors have different dimensions.
22 . The image display system according to claim 16 , wherein the driver circuit further includes an inverter to invert the phase of the voltage output signal.
23 . The image display system according to claim 16 , further comprising a display panel, wherein the interface driver circuit is a part of the display panel.
24 . The image display system according to claim 23 , further comprising a power supplier coupling to the display panel and supplying electrical power to the display panel.
25 . The image display system according to claim 16 , wherein the image display system is a mobile phone, a digital camera, a personal digital assistant (PDA), a notebook computer, a desktop computer, a television, a global positioning system (GPS), a car display, an aviation display monitor, a digital photo frame or a portable DVD player.