Thin film transistor and method for manufacturing thereof
A thin-film transistor (TFT) includes a gate electrode, a gate dielectric layer, a semiconductor layer, source/drain electrodes, a passivation layer and a protection layer. The gate electrode is disposed on a substrate. The gate dielectric layer covers the gate electrode and the substrate. The semiconductor layer is disposed on the gate dielectric layer and above the gate electrode. The semiconductor layer has a channel region disposed above the gate electrode and source/drain regions disposed at both sides of the channel region. The source/drain electrodes are disposed on the source/drain regions of the semiconductor layer and each has a barrier layer disposed on the source/drain regions of the semiconductor layer and a conductive layer disposed on the barrier layer. The passivation layer is disposed over the surface of the source/drain electrodes. The protection layer is disposed over the substrate, the passivation layer, and the channel region of the semiconductor layer.
1. A thin film transistor disposed on a substrate, comprising:
a gate electrode disposed on the substrate;
a gate dielectric layer covering the gate electrode and the substrate;
a patterned semiconductor layer disposed on the gate dielectric layer over the gate electrode, having a channel region disposed over the gate electrode and source/drain regions disposed at both sides of the channel region;
source/drain electrodes disposed on the source/drain regions of the patterned semiconductor layer, the source/drain electrodes comprising a stack of a patterned barrier layer and a patterned metal conductive layer, the patterned barrier layer being disposed on the source/drain regions of the patterned semiconductor layer, the patterned metal conductive layer being disposed on the patterned barrier layer and in contact with the patterned barrier layer;
a passivation layer made of a material consisting essentially of a metal nitride, the passivation layer covering a top surface of the patterned metal conductive layer, wherein the passivation layer has a thickness of 5-200 angstrom; and
a protection layer covering the passivation layer, the channel region of the semiconductor layer, and the substrate.
2. The thin film transistor according to claim 1 , wherein a material of the patterned semiconductor layer comprises amorphous silicon, microcrystalline silicon, or polycrystalline silicon.
3. The thin film transistor according to claim 1 , further comprising a patterned doped semiconductor layer disposed between the patterned semiconductor layer and the patterned barrier layer.
4. The thin film transistor according to claim 3 , wherein a material of the patterned doped semiconductor layer comprises N-type doped amorphous silicon, N-type doped microcrystalline silicon, or N-type doped polycrystalline silicon.
5. The thin film transistor according to claim 1 , wherein a material of the barrier layer comprises copper oxide, copper oxynitride, copper alloy oxide, or copper alloy oxynitride.
6. The thin film transistor according to claim 1 , wherein a material of the patterned metal conductive layer comprises copper, aluminum, or alloys thereof.
7. The thin film transistor according to claim 1 , wherein the material consisting essentially of the metal nitride comprises copper nitride, copper alloy nitride, nitrogen doped copper, or nitrogen doped copper alloy.
8. A unit structure of a semiconductor array substrate unit, each unit structure having at least a switch region and at least a capacitor region disposed on a substrate, the unit structure comprises:
a gate electrode disposed on the switch region;
a first electrode disposed on the capacitor region;
a gate dielectric layer covering the gate electrode, the first electrode and the substrate;
a patterned semiconductor layer disposed on the gate dielectric layer over the gate electrode, having a channel region disposed over the gate electrode and source/drain regions at both sides of the channel region;
source/drain electrodes disposed on the source/drain regions of the patterned semiconductor layer, the source/drain electrodes comprising a stack of a patterned barrier layer and a patterned metal conductive layer, the patterned barrier layer being disposed on the source/drain regions of the patterned semiconductor layer, the patterned metal conductive layer being disposed on the patterned barrier layer and in contact with the patterned barrier layer;
a second electrode disposed on the gate dielectric layer over the first electrode;
a passivation layer made of a material consisting essentially of a metal nitride, the passivation layer covering a top surface of the source/drain electrodes and a surface of the second electrode, wherein the passivation layer has a thickness of 5-200 angstrom;
a protection layer covering the passivation layer, the semiconductor layer, and the gate dielectric layer; and
a pixel electrode disposed on a portion of the protection layer, wherein the pixel electrode electrically connected to one of the source/drain electrodes and the second electrode.