Method and device for transmitting data packets

1. Method for transmitting data packets, comprising: writing to a first register of at least one descriptor of packets to be transmitted, each descriptor of packets to be transmitted comprising information representative of a status of each packet to be transmitted, the status of each packet indicating whether said packet is or is not to be transmitted, the at least one descriptor of packets to be transmitted being updated with:

at least an error descriptor when the at least an error descriptor is received before expiration of a timeout with the aid of an AND operation performed bitwise with the error descriptor received, and when the timeout expires, updating the corresponding descriptor of blocks to be transmitted with the aid of an AND operation performed bitwise with a descriptor of acknowledged packets;

determining a first packet of data to be transmitted on the basis of the content of said first register and recording of an identifier of the first packet of data to be transmitted in a second register; and transmitting a set of data packets based on the updated descriptor of packets to be transmitted.

2. Method according to claim 1 , wherein said determining the first packet is an elementary step performed in at most a number of clock cycles that is strictly less than the size of the first register expressed as a number of binary data.

3. Method according to claim 2 , wherein said determining the first packet is an elementary step performed in at most one clock cycle.

4. Method according to claim 1 , further comprising determining a number of consecutive packets to be transmitted with said first packet of data to be transmitted.

5. Method according to claim 4 , wherein said determining the number of consecutive packets to be transmitted is an elementary step performed in at most a number of clock cycles that is strictly less than the size of the first register expressed as a number of binary data.

6. Method according to claim 5 , wherein said determining the number of consecutive packets to be transmitted is an elementary step performed in at most one clock cycle.

7. Method according to claim 4 , wherein said determining the first packet and of determining the number of consecutive packets to be transmitted are simultaneous.

8. Method according to claim 1 , further comprising recording a number of consecutive packets to be transmitted in said second register.

9. Method according to claim 1 , wherein the reading of the second register brings about a purely electronic updating of the first register, of the status of each packet indicated as having to be transmitted by the second register.

10. Method according to claim 9 , wherein the reading of the second register and the updating of the corresponding first register are done in at most one clock cycle.

11. Method according to claim 1 , wherein said determining the first packet of data to be transmitted on the basis of the content of said first register and of recording the identifier of the first packet of data to be transmitted in the second register are repeated as long as the descriptor comprises information representative of a status corresponding to said packets to be transmitted.

12. Method according to claim 1 , wherein the packet corresponding to a status is identified, at least in part, by the position of an information representative of the status.

13. Method according to claim 1 , wherein the transmission of said set of data packets is performed on a wireless channel.

14. Device for transmitting data packets, comprising: a first register for recording at least one descriptor of packets to be transmitted, each descriptor of packets to be transmitted comprising information representative of a status of each packet to be transmitted, the status of each packet indicating whether said packet is or is not to be transmitted, the at least one descriptor of packets to be transmitted being updated with:

at least an error descriptor when the at least an error descriptor is received before expiration of a timeout with the aid of an AND operation performed bitwise with the error descriptor received, and when the timeout expires, updating the corresponding descriptor of blocks to be transmitted with the aid of an AND operation performed bitwise with a descriptor of acknowledged packets;

a filter for determining a first packet of data to be transmitted on the basis of the content of said first register and a second register for recording an identifier of the first packet of data to be transmitted; and a transmitter for transmitting a set of data packets based on the updated descriptor of packets to be transmitted.