System for displaying images
View Patent ↗A system for displaying images is provided. A capacitor type digital-to-analog converter is coupled between a first node and a second node and generates a first analog signal according to a digital signal with N bit data. An analogue buffer is coupled between the second node and a third node and generates a second analog signal according to the first analog signal and a bias voltage. A first switch is coupled between a predetermined voltage and the second node. A second switch is coupled between the first node and the third node. A third switch is coupled between the third node and an analog output signal. The second switch is turned on and the third switch is turned off when the first switch is turned on, and the first and second switches are turned off when the third switch is turned on.
1. A system for displaying images, comprising:
a digital-to-analog converting circuit for converting a digital signal with N bit data to an analog output signal, comprising:
a capacitor type digital-to-analog converter coupled between a first node and a second node, comprising a plurality of capacitors and switches and generating a first analog signal according to the digital signal, a first reference voltage and a second reference voltage;
an analogue buffer coupled between the second node and a third node for generating a second analog signal according to the first analog signal and a bias voltage, comprising:
a first transistor coupled between a predetermined voltage and the third node, having a first gate coupled to the second node; and
a second transistor coupled between a ground and the third node, having a second gate coupled to the bias voltage;
a first switch coupled between the predetermined voltage and the second node;
a second switch coupled between the first node and the third node; and
a third switch coupled between the third node and the analog output signal for transmitting the second analog signal as the analog output signal when the third switch is turned on,
wherein the second switch is turned on and the third switch is turned off when the first switch is turned on, and the first and second switches are turned off when the third switch is turned on.
2. The system as claimed in claim 1 , wherein the capacitor type digital-to-analog converter further comprises:
a capacitor switch network, comprising N input circuits corresponding to each bit data of the input signal respectively, wherein each input circuit comprises:
a bit switch, which is selectively coupled to one of the first and second reference voltages according to the corresponding bit data;
a first mode switch, which is selectively coupled to one of the bit switch and the first node according to a reset signal; and
a first capacitor coupled between the first mode switch and the second node;
a second mode switch, which is selectively coupled to one of the first reference voltage and the first node according to the reset signal; and
a second capacitor coupled between the second mode switch and the second node.
3. The system as claimed in claim 2 , wherein the first switch is turned on when the reset signal is at a first logic level.
4. The system as claimed in claim 3 , wherein the first and second mode switches are coupled to the first node when the reset signal is at the first logic level.
5. The system as claimed in claim 3 , wherein the first switch is turned off when the reset signal is at a second logic level.
6. The system as claimed in claim 5 , wherein the first mode switch is coupled to the bit switch and the second mode switch is coupled to the first reference voltage when the reset signal is at the second logic level.
7. The system as claimed in claim 2 , the bit switch is coupled to the first reference voltage when the bit data is at a high logic level, and the bit switch is coupled to the second reference voltage when the bit data is at a low logic level.
8. The system as claimed in claim 7 , wherein the first reference voltage is greater than the second reference voltage.
9. The system as claimed in claim 2 , wherein the capacitor switch network further comprises (N−1) third capacitors coupled between the two adjacent input circuits, respectively.
10. The system as claimed in claim 9 , wherein a capacitance ratio of the first capacitor to the second capacitor is 1:1, and a capacitance ratio of the first capacitor to the third capacitor is 1:2.
11. The system as claimed in claim 10 , wherein the capacitor type digital-to-analog converter is a C-2C ladder digital-to-analog converter.
12. The system as claimed in claim 1 , wherein the capacitances of the first capacitors are increased by a power of 2 in a sequence, which corresponds to a bit sequence from a most significant bit (MSB) to a least significant bit (LSB) of the digital signal.
13. The system as claimed in claim 12 , wherein a capacitance ratio of the first capacitor to the second capacitor is 1:2 (N−1) .
14. The system as claimed in claim 13 , wherein the capacitor type digital-to-analog converter is a binary-weighted digital-to-analog converter.
15. The system as claimed in claim 1 , further comprising a display panel, wherein the digital-to-analog converting circuit forms a portion of the display panel.
16. The system as claimed in claim 1 , further comprising an electronic device, wherein the electronic device comprises:
a display panel; and
a power supply coupled to the display panel and operative to provide power to the display panel.
17. The system as claimed in claim 16 , wherein the electronic device is a mobile phone, digital camera, personal data assistant (PDA), notebook computer, desktop computer, television, car display, aerial display, global positioning system (GPS), digital photo frame or portable DVD player.